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LMX2325 Datasheet(PDF) 18 Page - National Semiconductor (TI) |
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LMX2325 Datasheet(HTML) 18 Page - National Semiconductor (TI) |
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18 / 22 page ![]() Application Information (Continued) MEASUREMENT RESULTS (Example 1) TLW12339 – 47 FIGURE 5 PLL Reference Spurs The reference spurious level is k b74 dBc due to the loop filter attenuation and the low spurious noise level of the LMX2315 TLW12339 – 49 FIGURE 6 PLL Phase Noise 10 kHz Offset The phase noise level at 10 kHz offset is b80 dBcHz TLW12339 – 48 FIGURE 7 PLL Phase Noise 1 kHz Offset The phase noise level at 1 kHz offset is b795 dBcHz TLW12339 – 50 FIGURE 8 Frequency Jump Lock Time Of concern in any PLL loop filter design is the time it takes to lock in to a new frequency when switching channels Fig- ure 8 shows the switching waveforms for a frequency jump of 865 MHz to 915 MHz By narrowing the frequency span of the HP53310A Modulation Domain Analyzer enables evaluation of the frequency lock time to within g500 Hz The lock time is seen to be less than 500 ms for a frequency jump of 50 MHz http www nationalcom 18 |
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