2.2.5 R_OPT[2:0]

Reference Oscillator Optimization

R[17:15]

The R_OPT control words are used to optimize the performance of the reference buffer circuit for best Phase Noise and power

consumption performance based on the frequency of the reference source.

R_OPT[2:0]

Optimization Frequency

Range

0

5 MHz–50 MHz

7

50 MHz–104 MHz

1-6

Reserved — Do not use.

2.3 N REGISTER

The N register contains the PD (Power-Down), NA_CNTR, and NB_CNTR control words. The NA_CNTR, and NB_CNTR control

words are used to setup the programmable feedback divider. The PWR-DN control word is used to switch the device between the

normal operating mode and various power-down modes.

Register

Most Significant Bit

SHIFT REGISTER BIT LOCATION

Least Significant Bit

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Data Field

ADDR

N

NB_CNTR [9:0]

NA_CNTR [4:0]

PD [1:0]

0

2.3.1 PD[1:0]

Power-Down

N[2:1]

The PD control word is used to switch the device between the normal operating mode and various power-down modes.

PD [1:0]

Operating Mode

0

Normal Operation

1

Synchronous Power-down

2

Counter Reset

3

Asynchronous Power-down

2.3.2 NA_CNTR[4:0]

A Counter

N[7:3]

The NA_CNTR control word is used to program the A counter. The A counter is a 5-bit swallow counter used in the programmable

feedback divider. The A counter can be programmed to values ranging from 0 to 31. See Section 1.4 for details on how the value

of the A counter should be selected.

A Counter Value

NA_CNTR[4:0]

0

00000

1

00001

•

•••••

31

11111

2.3.3 NB_CNTR[9:0]

B Counter

N[17:8]

The NB_CNTR control word is used to program the B counter. The B counter is a 10-bit binary counter used in the programmable

feedback divider. The B counter can be programmed to values ranging from 3 to 1023. See Section 1.4 for details on how the

value of the B counter should be selected.

B Counter Value

NB_CNTR[9:0]

3

0000000011

4

0000000100

•

••••••••••

1023

1111111111

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