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LMX2346TM Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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LMX2346TM Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 27 page ![]() Pin Descriptions (Continued) Pin Name Pin Number I/O Description I/O Circuit Configuration 16-Pin CSP 16-Pin TSSOP F INB 5 7 I RF prescaler complementary input. For single ended operation, this pin should be AC grounded. The LMX2346/7 can be driven differentially when a bypass capacitor is omitted. F IN 6 8 I RF PLL prescaler input. Small signal input from the VCO. CLOCK 8 9 I High impedance CMOS Clock input. Data is clocked in on the rising edge, into the 18-bit shift register. DATA 9 10 I Binary serial data input. Data entered MSB first. LSB is control bit. High impedance CMOS input. LE 10 11 I Latch Enable input. When Latch Enable transitions HIGH, data stored in the 18-bit shift register is loaded into one of the 2 control registers, based on the address bit. High impendance CMOS input. CE 11 12 I Chip Enable input. Provides logical power-down control of the device. Pull-up to V CC if unused. High impedance CMOS input. www.national.com 3 |
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