STR71XF datasheet(12/49 Pages) STMICROELECTRONICS

12 / 49 page

STR71xF - INTRODUCTION

12/49

P2.3/CS.3

I/O

8mA X

Port 2.3

External Memory Interface: Select Memory

Bank 4 output

P2.4/A.20

I/O

8mA X

Port 2.4

External Memory Interface: address bus

P2.5/A.21

I/O

8mA X

Port 2.5

P2.6/A.22

I/O

8mA X

Port 2.6

BOOTEN

Boot control input. Enables sampling of BOOT[1:0] pins

P2.7/A.23

I/O

8mA X

Port 2.7

External Memory Interface: address bus

P2.8

I/O pu CT X 4mA X

Port 2.8

External interrupt INT2

N.C.

Not connected (not bonded)

N.C.

Not connected (not bonded)

VSS

Ground voltage for digital I/Os

V33

Supply voltage for digital I/Os

P2.9

I/O pu CT X 4mA X

Port 2.9

External interrupt INT3

P2.10

I/O pu CT X4mA X

Port

2.10

External interrupt INT4

P2.11

I/O pu CT X4mA X

Port

2.11

External interrupt INT5

P2.12

I/O pu CT

4mA X

Port

2.12

P2.13

I/O pu CT

4mA X

Port

2.13

P2.14

I/O pu CT

4mA X

Port

2.14

P2.15

I/O pu CT

4mA X

Port

2.15

JTDI

JTAG Data input. External pull-up required.

JTMS

JTAG Mode Selection Input. External pull-up required.

JTCK

JTAG Clock Input. External pull-up or pull-down re-

quired.

JTDO

8mA

JTAG Data output. Note: Reset state = HiZ.

JTRST

ITT

JTAG Reset Input. External pull-up required.

Reserved, must be forced to ground.

TEST

Reserved, must be forced to ground.

N.C.

Not connected (not bonded)

TEST

Reserved, must be forced to ground.

N.C.

Not connected (not bonded)

Table 3. STR710 Pin Description

Pin n°

Pin Name

Input

Output

Main

function

(after

reset)

Alternate function

STR71XF Datasheet(PDF) 12 Page - STMicroelectronics

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