ML610401 datasheet(13/27 Pages) LAPIS

13 / 27 page

FEDL610403-04

ML610401/ML610402/ML610403

13/27

Pin name

I/O

Description

Primary/

Secondary/

Tertiary

Logic

RC oscillation type A/D converter

IN0

Channel 0 oscillation input pin. This pin is used as the secondary function

of the P30 pin.

Secondary

—

CS0

Channel 0 reference capacitor connection pin. This pin is used as the

secondary function of the P31 pin.

Secondary

—

RCT0

Resistor/capacitor sensor connection pin of Channel 0 for measurement.

This pin is used as the secondary function of the P34 pin.

Secondary

—

RS0

This pin is used as the secondary function of the P32 pin which is the

reference resistor connection pin of Channel 0.

Secondary

—

RT0

Resistor sensor connection pin of Channel 0 for measurement. This pin is

used as the secondary function of the P33 pin.

Secondary

—

RCM

RC oscillation monitor pin. This pin is used as the secondary function of

the P35 pin.

Secondary

—

IN1

Oscillation input pin of Channel 1. This pin is used as the secondary

function of the P44 pin.

Secondary

—

CS1

Reference capacitor connection pin of Channel 1. This pin is used as the

secondary function of the P45 pin.

Secondary

—

RS1

Reference resistor connection pin of Channel 1. This pin is used as the

secondary function of the P46 pin.

Secondary

—

RT1

Resistor sensor connection pin for measurement of Channel 1. This pin is

used as the secondary function of the P47 pin.

Secondary

—

LCD drive signal

COM0-4

Common output pins.

—

SEG0-13

Segment output pins.

—

SEG14-17

Segment output pin. These pins are for the ML610402/ML610403, but are

not provided in the ML610401.

—

SEG18-21

O Segment output pin. These pins are for the ML610403, but are not

provided in the ML610401/ML610402.

—

LCD driver power supply

VL1

—

VL2

—

VL3

—

Power supply pins for LCD bias (internally generated or positive power

supply pin

connected ). Depending on LCD Bias setting and VDD voltage

level, VDD or VDDL or capacitor is connected. For details of the connection

method, see user’s manual.

—

Power supply pins for LCD bias (internally generated). Capacitors C12 is

connected between C1 and C2.

—

For testing

TEST0

I/O Input/output pin for testing. A pull-down resistor is internally connected.

—

Power supply

VSS

— Negative power supply pin.

—

VDD

— Positive power supply pin for I/O, internal regulator, battery low detector,

and power-on reset.

—

VDDL

— Positive power supply pin (internally generated) for internal logic.

Capacitor CL (see Appendix C measuring circuit 1) is connected between

this pin and VSS.

—

ML610401 Datasheet(PDF) 13 Page - LAPIS Semiconductor Co., Ltd.

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