AM29LV256M datasheet(40/70 Pages) AMD

40 / 70 page

Am29LV256M

September 15, 2003

D A T A SH EET

Figure 6.

Program Suspend/Program Resume

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does

not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Tables 11 and

12 show the address and data requirements for the

chip erase command sequence.

When the Embedded Erase algorithm is complete, the

device returns to the read mode and addresses are no

longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, or DQ2.

Refer to the Write Operation Status section for infor-

mation on these status bits.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once the device has returned to reading

array data, to ensure data integrity.

Figure 10 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 18 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 12 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

The device does

not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise erasure may begin. Any sector erase

address and command following the exceeded

time-out may or may not be accepted. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector

Erase command is written. Any command other than

Se c t or Er a s e or Er a s e Su s pe nd dur i n g the

time-out period resets the device to the read

mode. The system must rewrite the command se-

quence and any additional addresses and commands.

Note that the SecSi Sector, autoselect, and CFI func-

tions are unavailable when an erase operation in is

progress.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Program Operation

or Write-to-Buffer

Sequence in Progress

Write Program Suspend

Command Sequence

Command is also valid for

Erase-suspended-program

operations

Autoselect and SecSi Sector

read operations are also allowed

Data cannot be read from erase- or

program-suspended sectors

Write Program Resume

Command Sequence

Read data as

required

Done

reading?

Yes

Write address/data

XXXh/3030h

Device reverts to

operation prior to

Program Suspend

Write address/data

XXXh/B0B0h

Wait 15 ms

AM29LV256M Datasheet(PDF) 40 Page - Advanced Micro Devices

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