COP425C datasheet(8/24 Pages) NSC

8 / 24 page

Functional Description (Continued)

The SIO register functions as a 4-bit serial-inserial-out shift

binary counter (depending on the contents of the EN regis-

ter) Its contents can be exchanged with A

The XAS instruction copies C into the SKL latch In the

counter mode SK is the output of SKL in the shift register

mode SK outputs SKL ANDed with the clock

EN is an internal 4-bit register loaded by the LEI instruction

The state of each bit of this register selects or deselects the

particular feature associated with each bit of the EN regis-

ter

0 The least significant bit of the enable register EN0 se-

lects the SIO register as either a 4-bit shift register or a

4-bit binary counter With EN0 set SIO is an asynchro-

nous binary counter decrementing its value by one upon

each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI

input Each pulse must be at least two instruction cycles

wide SK outputs the value of SKL The SO output equals

the value of EN3 With EN0 reset SIO is a serial shift

data present at SI goes into the least significant bit of

SIO SO can be enabled to output the most significant bit

of SIO each cycle time The SK outputs SKL ANDed with

the instruction cycle clock

1 With EN1 set interrupt is enabled Immediately following

an interrupt EN1 is reset to disable further interrupts

2 With EN2 set the L drivers are enabled to output the data

in Q to the L IO port Resetting EN2 disables the L driv-

ers placing the L IO port in a high-impedance input

state

TLDD5259 – 4

FIGURE 3 InputOutput Timing Diagrams (divide by 8 mode)

TLDD5259 – 5

FIGURE 4 Microbus Read Operation Timing

TLDD5259 – 6

FIGURE 5 Microbus Write Operation Timing

COP425C Datasheet(PDF) 8 Page - National Semiconductor (TI)