CS5451 datasheet(8/14 Pages) ETC

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CS5451

DS458PP4

2.2

Performing Measurements

The converter outputs are transferred in 16-bit

signed (two’s complement) data formats as a per-

centage of full scale. Table 1 below illustrates the

ideal relationship between the differential voltage

presented any one of the input channels and the

corresponding output code. Note that for the cur-

rent channels, the state of the GAIN input pin is as-

sumed to driven low such that the PGA gain on the

current channels is 1x. If the PGA gain of the cur-

rent channels is set to 20x, a +40 mV differential

voltage is presented across any pair of “IINk+” and

“IINk-” pins (k = 1, 2, 3) would cause a (nominal)

output code of 32767.

Table 1. Nominal Relationship for Differential Input

Voltage vs. Output Code, for all channels. (Assume PGA

gain is set to 1x.)

2.3

High Rate Digital Filters

If the OWRS pin is set to logic low, the high-rate

filters are implemented as fixed sinc3 filters with

the following transfer function:

This filter samples the modulator bit stream at

XIN/8 Hz and decimates to XIN/2048 Hz.

If the OWRS pin is set to logic high, then the trans-

fer function is

The above filter samples the modulator bit stream

at XIN/8 Hz and decimates to XIN/1024 Hz.

2.4

Serial Interface

The CS5451 communicates with a target device via

a master serial data output port. Output data is pro-

vided on the SDO output synchronous with the

SCLK output. A third output, FSO, is a framing

signal used to signal the start of output data. These

three outputs will be driven as long as the SE (serial

Differential Input

Voltage (mV)

Output Code

(hexadecimal)

Output Code

(decimal)

+800

7FFF

32767

0.0122 to 0.0366

0001

-0.0122 to 0.0122

0000

-0.0122 to -0.0366

FFFF

-1

-800

8000

-32768

()

256

–

----------------------







()

128

–

----------------------







SCLK

FSO

SDO

Channel 1 V

Channel 2 I

Channel 3 I

Channel 2 V

Channel 3 V

Channel 1 I

Each data segment

is 16 bits long.

96 SCLKs

Figure 3. Serial Port Data Transfer

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