COP445C datasheet(9/24 Pages) NSC

9 / 24 page

Functional Description (Continued)

3 EN3 in conjunction with EN0 affects the SO output With

EN0 set (binary counter option selected) SO will output

the value loaded into EN3 With EN0 reset (serial shift

output of the SIO shift register outputting serial shifted

data each instruction time Resetting EN3 with the serial

shift register option selected disables SO as the shift reg-

ister output data continues to be shifted through SIO and

can be exchanged with A via an XAS instruction but SO

remains set to ‘‘0’’

INTERRUPT

The following features are associated with interrupt proce-

dure and protocol and must be considered by the program-

mer when utilizing interrupts

a The interrupt

once recognized as explained below

pushes the next sequential program counter address

(PCa1) onto the stack Any previous contents at the bot-

tom of the stack are lost The program counter is set to

hex address 0FF (the last word of page 3) and EN1 is

reset

b An interrupt will be recognized only on the following con-

ditions

1 EN1 has been set

2 A low-going pulse (‘‘1’’ to ‘‘0’’) at least two instruction

cycles wide has occurred on the IN1 input

3 A currently executing instruction has been completed

4 All successive transfer of control instructions and suc-

cessive LBIs have been completed (eg if the main

program is executing a JP instruction which transfers

program control to another JP instruction the interrupt

will not be acknowledged until the second JP instruc-

tion has been executed)

c Upon acknowledgement of an interrupt the skip logic

status is saved and later restored upon popping of the

stack For example if an interrupt occurs during the exe-

cution of ASC (Add with Carry Skip on Carry) instruction

which results in carry the skip logic status is saved and

program control is transferred to the interrupt servicing

routine at hex address 0FF At the end of the interrupt

routine a RET instruction is executed to pop the stack

and return program control to the instruction following the

original ASC At this time the skip logic is enabled and

skips this instruction because of the previous ASC carry

Subroutines should not be nested within the interrupt

service routine since their popping of the stack will en-

able any previously saved main program skips interfering

with the orderly execution of the interrupt routine

d The instruction at hex address 0FF must be a NOP

e An LEI instruction may be put immediately before the

RET instruction to re-enable interrupts

MICROBUS INTERFACE

The COP444C424C has an option which allows it to be

used as a peripheral microprocessor device inputting and

outputting data from and to a host microprocessor (mP)

IN1 IN2 and IN3 general purpose inputs become Microbus

compatible read-strobe chip-select and write-strobe lines

respectively IN1 becomes RD

a logic ‘‘0’’ on this input

will cause Q latch data to be enabled to the L ports for input

to the uP IN2 becomes CS

a logic ‘‘0’’ on this line se-

lects the COP444C424C as the uP peripheral device by

enabling the operation of the RD and WR lines and allows

for the selection of one of several peripheral components

IN3 becomes WR

a logic ‘‘0’’ on this line will write bus

data from the L ports to the Q latches for input to the

COP444C424C G0 becomes INTR a ‘‘ready’’ output reset

by a write pulse from the uP on the WR line providing the

‘‘handshaking’’ capability necessary for asynchronous data

transfer between the host CPU and the COP444C424C

This option has been designed for compatibility with Nation-

al’s Microbus

a standard interconnect system for 8-bit

parallel data transfer between MOSLSI CPUs and interfac-

ing devices (See Microbus National Publication) The func-

tioning and timing relationships between the signal lines af-

fected by this option are as specified for the Microbus inter-

face and are given in the AC electrical characteristics and

shown in the timing diagrams (

Figures 4 and 5 ) Connection

of the COP444C424C to the Microbus is shown in

Figure 6

TLDD5259 – 7

FIGURE 6 Microbus Option Interconnect

TABLE I Enable Register Modes

Bits EN0 and EN3

EN0 EN3

SIO

Shift

Input to Shift

If SKLe1SKeclock

If SKLe0SKe0

Shift

Input to Shift Serial If SKLe1SKeclock

out

If SKLe0SKe0

Binary

Input to

SKeSKL

Counter

Binary

Input to

SKeSKL

Counter

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