L3GD20H datasheet(14/52 Pages) STMICROELECTRONICS

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Mechanical and electrical specifications

L3GD20H

14/52

DocID023469 Rev 2

2.4.2

I2C - Inter IC control interface

Subject to general operating conditions for Vdd and Top.

Figure 4. I2C slave timing diagram(e)

Table 7. I2C slave timing values

Symbol

Parameter

I2C standard mode(1)

I2C fast mode (1)

Unit

Min.

Max.

Min.

Max.

(SCL)

SCL clock frequency

100

400

kHz

w(SCLL)

SCL clock low time

4.7

1.3

μs

w(SCLH)

SCL clock high time

4.0

0.6

su(SDA)

SDA setup time

250

100

h(SDA)

SDA data hold time

3.45

0.9

μs

r(SDA)

r(SCL)

SDA and SCL rise time

1000

20 + 0.1C

(2)

300

f(SDA)

f(SCL)

SDA and SCL fall time

300

20 + 0.1C

(2)

300

h(ST)

START condition hold time

0.6

μs

su(SR)

Repeated START condition

setup time

4.7

0.6

su(SP)

STOP condition setup time

0.6

w(SP:SR)

Bus free time between STOP

and START condition

4.7

1.3

Data based on standard I

C protocol requirement, not tested in production.

Cb = total capacitance of one bus line, in pF.

Measurement points are done at 0.2· Vdd_IO and 0.8· Vdd_IO, for both ports.

SDA

SCL

tf(SDA)

tsu(SP)

tw(SCLL)

tsu(SDA)

tr(SDA)

tsu(SR)

th(ST)

tw(SCLH)

th(SDA)

tr(SCL)

tf(SCL)

tw(SP:SR)

START

REPEATED

START

STOP

START

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