VITESSE

SEMICONDUCTOR CORPORATION

reliminary Datasheet

SC8164

2.488 Gbit/sec to 2.7Gbit/sec

1:16 SONET/SDH Demux

G52239-0, Rev. 3.3

 VITESSE SEMICONDUCTOR CORPORATION

Page 5

5/17/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Figure 7: Differential and Single Ended Input and Output Voltage Measurement

Table 1: AC Characteristics

Parameters

Description

Min

Max

Units

Conditions

Data valid from falling

edge of CLK16O+

0800

ps.

CLK32O transition from

falling edge of CLK16O+

01.0

ns.

D[15:0]+/- rise and fall

times

—

400

ps

20% to 80% into 50 Ohm load.

See Figure 7

CLK16O+/- rise and fall

times

—

250

ps

20% to 80% into 50 Ohm load.

See Figure 7

CLK16O+/- duty cycle

distortion

45

55

% of

clock

cycle

High speed clock input at 2.488GHz

DI+ setup time with respect

to falling edge of

HSCLKI+

100

—

ps

DI+ hold time with respect

to falling edge of

HSCLKI+

75

—

ps

HSCLKI+/- duty cycle

distortion

40

60

% of

clock

cycle

Single

Ended

Swing

Differential

Swing

=

α

=

α

a

a

b

b

* Differential swing

(α) is specified as | b - a | ( or | a - b | ), as is the single ended swing.

Differential swing is specified as equal in magnitude to single ended swing.