PC97338 datasheet(195/221 Pages) NSC

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— VIL = VSS, VIH = VDD

— VDD = 3.3V

— FCR bit 0 of SCC1 and SCC2 are 1 (16550

mode - FIFO enabled)

3. When PCR bit 3 is 1, and the ECP is enabled (bit

2 of PCR is 1) the clock multiplier and the ECP

clock are not stopped.

7.1.2

Recommended Power-Down

Methods - Group 2

Use the power-down methods in Group 2 to place the

chip in any desired combination of the following pow-

er-down modes:

Mode 1:Parallel Port (SPP/EPP/ECP) is powered-

down, providing a possible saving of up to 5 mA.

Mode 2: SCCs are powered-down, providing a possi-

ble saving of up to 5 mA.

Mode 3:FDC is powered-down, providing a possible

saving of up to 4 mA.

7.1.3

Special Power-Down Cases

The FDC can be powered down by executing the

MODE command or by setting bit 6 of DSR to high.

This is equivalent to the Mode 2 described in the pre-

vious section. See Sections 3.3.7 and 3.6.7.

When the parallel port is enabled in Extended Capa-

bility Port (ECP) mode (bit 2 of the Printer Control

configuration Register (PCR) is 1), powering down by

setting bit 2 of the Power and Test configuration Reg-

ister (PTR) will not stop the clock of the ECP. Bit 3 of

PCR must also be 0 before the internal clock multipli-

er to the ECP can stop. See Sections 2.3.4 and 2.3.6.

7.2

POWER-UP

The chip powers up with all modules disabled, as de-

scribed in Mode 2, above.

7.2.1

The Clock Multiplier

The source of all internal clocks in the chip can be ei-

ther an external 48 MHz clock on the X1 pin, or the on-

chip clock multiplier.

The on-chip clock multiplier is fed by applying either a

14.31818 MHz or a 24 MHz clock on the same X1 pin.

It generates two internal clocks: 24 MHz and 48 MHz.

The 24 MHz clock is needed for SCC1, the FDC and

the Parallel Port. The 48 MHz clock is needed for

SCC2 and the FDC when it supports 2Mbps data

rates, as set by bit 1 of the Tape, SCCs and Parallel

Port (TUP) register. See Section 2.3.8.

After power-up or reset, the clock multiplier is dis-

abled.

Clock Multiplier Functionality

The on-chip clock multiplier starts working, when it is

enabled via the clock multiplier enable bit (bit 2 of the

CLK register, at index 51), i.e., when it changes from

0 to 1. This bit can also disable the on-chip clock mul-

tiplier and its output clock after the multiplier is en-

abled.

Once enabled, the output clock is frozen to a steady

logic level until the multiplier can provide a stable out-

put clock that meets all requirements; then it starts

toggling.

On power-on, when VDD is applied, the chip wakes-up

with the on-chip clock multiplier disabled. The input

and output clocks of the on-chip clock multiplier may

toggle regardless of the state of the Master Reset

(MR) pin (they can toggle while MR is active). The on-

chip clock multiplier must have a toggling input clock.

If the input clock is not toggling, the on-chip clock mul-

tiplier waits until this input clock starts toggling.

Bit 3 of the CLK register is the Valid Clock Multiplier

status bit. It is read only. While stabilizing, the output

clock is frozen to a steady logic level, and the status

bit is cleared to 0 to indicate a frozen clock. When the

on-chip clock multiplier is stable, the output clock

starts toggling and the status bit is set to 1. The status

bit tells the software, when the clock multiplier is

ready. The software should poll this status bit and ac-

tivate (enable) the FDC, Parallel Port, SCCs and in-

frared interface only if it is 1.

When the multiplier is enabled for the first time after

power-on, more time is required until this status bit is

set to 1.

The on-chip clock multiplier and its output clock do not

consume power, when they are disabled.

Clock Multiplier Specifications

Wake-up time, from valid VDD (2.1V minimum) tog-

gling input clock and multiplier enabled, until clock is

stable is 2.6 msec (maximum).

Tolerance (long term deviation) of the multiplier out-

put clock, relative to input clock is

±110 ppm.

Total tolerance is therefore

± (input clock tolerance +

110 ppm).

Cycle by cycle variance is 0.4 nsec (maximum).

7.2.2

Chip Power-Up Procedure

To ensure proper operation, do the following, after

power-up:

1. Set bits 2,1 and 0 of the Clock Control configura-

tion (CLK) register at index 51, according to the

external clock source used. See Table 107.

Bits 2,1 and 0 may be written in a single write cy-

cle.

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