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PC97338 Datasheet(PDF) 207 Page - National Semiconductor (TI) |
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PC97338 Datasheet(HTML) 207 Page - National Semiconductor (TI) |
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207 / 221 page ![]() 207 www.national.com Note 1: tCWN is the nominal pulse width of the modulation signal for Sharp-IR and CEIR modes. It is determined by the MCPW [2-0] and TXHSC bits in the IRTXMC and RCCFG registers. Note 2: tCPN is the nominal period of the modulation signal for Sharp-IR and CEIR modes. It is determined by the MCFR [4-0] and TXHSC bits in the IRTXMC and RCCFG registers. Note 3: tMMIN and tMMAX define the time range within which the period of the incoming subcarrier signal has to fall in order for the signal to be accepted by the receiver. These time values are determined by the content of register IRRXDC and the setting of bit RXHSC in the RCCFG register. Note 4: tBTN is the nominal bit time in UART, Sharp-IR, SIR, MIR and CEIR modes. Note 5: tMWN is the nominal pulse width for MIR mode. It is determined by the MPW [3-0] and MDRS bits in the MIR_PW and IRCR2 registers. Note 6: The receiver pulse width requirements for various jitter values can be obtained by assuming a linear pulse-width/jitter relationship. For example, if the jitter is +/- 10 ns, the width of a single pulse must fall between 84 and 165 ns. Note 7: The WRITE Signal will not change from low to high before DSTRB or ASTRB changes from low to high. Note 8: D7-0 is assumed to be valid 15 ns or more before WR becomes active. Note 9: When WAIT is low, tWSTa and tWWa are measured from the high-to-low transition of WR or RD; otherwise they are measured from the high-to-low transition of WAIT. 8.4.2 Timing Diagrams FIGURE 91. Clock Timing tECHL Figures 107, 108 BUSY or AFD Delay After STB or ACK Inactive 0 35 ms tECLL Figures 107, 108 STB or ACK Active After BUSY or AFD Falling Edge 0ns MISCELLANEOUS TIMING tISS Figure 109 IRQn Signal Delay From SIRQI1,2,3 25 ns tCSD Figure 110 CS1-0 Signals Delay From A15-0, WR and RD 25 ns tMRW Figure 111 Master Reset Pulse Width 22 µs tMRF Figure 111 Output Signals Floating From Reset Active 700 ns tMRCia Figure 111 Output Signals Inactive From Reset Active 300 ns Symbol Figure Parameter Min Max Unit X1 tCL tCH |
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