PC97338 datasheet(218/221 Pages) NSC

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FAR

The Function Address configuration Register.

FBAH

The register that holds the High byte of the

Base Address of the Floppy Disc Controller

(FDC).

FBAL

The register that holds the Low byte of the

Base Address of the Floppy Disk Controller

(FDC).

FCR

The Function Control configuration Register or

the FIFO Control Register for SCCs.

FDC

Floppy Disk Controller.

FER

The Function Enable configuration Register.

FIFO

Data register (FIFO queue) of the Floppy Disk

Controller (FDC)

IER

The Interrupt Enable Register for the SCCs.

Index

The Index register is a pointer that is used to

address other registers.

Infrared.

IRCFG1, IRCFG3 and IRCFG4

Infrared module Configuration registers for the

SCC2.

IRCR1, IRCR2 and IRCR3

Infrared Module Control Registers 1, 2 and 3

for the SCC2.

IrDA

Infrared Data Association.

IrDA mode

In this mode, the Chip provides the Infrared

Data Association standard compliant inter-

face.

IRQ

Interrupt Request.

IRRXDC

Infrared Receiver Demodulator Control regis-

ter for the SCC2.

IRTXMC

Infrared Transmitter Modulator Control register

for the SCC2.

ISA

Industry Standard Architecture.

LBGD(H) and LBGD(L)

Legacy Baud rate Generator Divisor port

(High and Low bytes) for the SCC2.

LCR

Line Control Register for SCCs.

Legacy

A colloquial description usually referring to

older devices or systems that are not Plug and

Play compatible.

Legacy mode

In this mode, the interrupts and the base ad-

dresses of the FDC, SCC1, SCC2 and the

parallel port of the Chip are configured as in

earlier SuperI/O chips. This mode is config-

ured via bit 3 of Plug and Play configuration

LFSR

The Linear Feedback Shift Register. In Plug

and Play mode, this register is used to pre-

pare the chip for operation in Plug and Play

(PnP) mode.

LSR

Line Status Register for SCCs.

MCR

Modem Control Register for SCCs.

MRID

Module Revision ID register for the SCC2.

MSR

Main Status Register of the Floppy Disk Con-

troller (FDC) or Modem Status Register for

SCCs.

Non-Extended UART Operation Modes

These UART operation modes support only

UART operations that are standard for 15450

or 16550A devices.

PBAH

The register that holds the High byte of the

Base Address of the Parallel port.

PBAL

The register that holds the Low byte of the

Base Address of the Parallel port.

PCR

The Parallel port Control configuration Regis-

ter.

Plug and Play (PnP)

A design philosophy and a set of specifica-

tions that describe hardware and software

changes to the PC and its peripherals that au-

tomatically identify and arbitrate resource re-

quirements among all devices and buses on

the system.

PMC

The Power Management Control configuration

PnP

Plug and Play.

PC97338 Datasheet(PDF) 218 Page - National Semiconductor (TI)

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