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PC97338 Datasheet(PDF) 219 Page - National Semiconductor (TI) |
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PC97338 Datasheet(HTML) 219 Page - National Semiconductor (TI) |
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219 / 221 page  219 www.national.com PnP mode In this mode, the interrupts, the DMA chan- nels and the base address of the FDC, SCC1, SCC2 and the Parallel Port of the Chip are ful- ly plug and play. This mode is configured via bit 3 of Plug and Play configuration register 0 (PNP0). PNP0, PNP1 and PNP2 Plug and Play configuration registers 0 through 2. P_MDR Pipeline Mode Register for SCCs. PIO Programmable Input/Output. ppm Parts per million. PPM Parallel Port Multiplexor or Multiplexed. PPM mode In this mode, the Parallel Port pins of the chip serve as FDC pins. Precompensation Also called write precompensation, is a way of preconditioning the WDATA output signal to adjust for the effects of bit shift on the data as it is written to the disk surface. PTR The Power and Test configuration Register. RSR The Receiver Shift Register for SCCs. This register if for internal use only. SBAH The register that holds the High byte of the Base Address, of the Super I/O chip. SBAL The register that holds the Low byte of the Base Address, of the Super I/O chip. SCCs Serial Communciation Controllers. SCF0, SCF1 and SCF2 The Configuration registers that configure the Super I/O chip. SCR Scratch Register for SCCs. SH_LCR Shadow of the Line Control Register (LCR) for the SCC2 for read operations. SHARP-IR SHARP Infrared. SHARP-IR mode In this mode, the Chip provides SHARP Infra- red interface. This mode is configured via the IRC register. SID Super I/O ID, the configuration register that holds the identity of the Super I/O chip. SIO Super I/O, sometimes used to refer to a chip that has Super I/O capabilities. SIR Serial Infrared. SIR_PW SIR Pulse Width control for the SCC2. SIRQ1, SIRQ2 and SIRQ3 These configuration registers describe the SIRQI1, SIRQI2 and SIRQI3 functions, which determine how Interrupt Requests are han- dled. SPP The Standard Parallel Port configuration of the Parallel Port device supports the Compatible SPP mode and the Extended PP mode. SRA and SRB Status Registers A and B of the Floppy Disk Controller (FDC). ST0, ST1, ST2 and ST3 Status registers 0, 1, 2 and 3 of the Floppy Disk Controller (FDC). STR Status Register of the parallel port. TDR Tape Drive Register of the Floppy Disk Con- troller (FDC). TFIFO Test FIFO for the parallel port in Extended Ca- pabilities Port mode. TXDR The Transmitter Data Register for SCCs. TUP The Tape drive, SCCs, Parallel port configura- tion register. S1BAH The configuration register that holds the High byte of the Base Address of SCC1. S1BAL The configuration register that holds the Low byte of the Base Address of SCC1. S2BAH The configuration register that holds the High byte of the Base Address of SCC2. S2BAL The configuration register that holds the Low byte of the Base Address of SCC2. UART Universal Asynchronous Receiver Transmitter. |
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