| Electronic Components Datasheet Search |
|
L99MD01 Datasheet(PDF) 25 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
L99MD01 Datasheet(HTML) 25 Page - STMicroelectronics |
|
25 / 54 page ![]() L99MD01 Functional description of the SPI Doc ID 17242 Rev 6 25/54 The <Write Mode> and <Read Mode> operations allow access to the RAM of the device, i. e. write to control registers or read status information. A <Read and Clear Status> operation addressed to a device specific status register reads back and subsequently clear this status register. A <Read and Clear Status> operation with address 3FH clears all status registers at a time and reads back the <Configuration> register. A <Read and Clear Status> operation addressed to an unused RAM address register is identical to a <Read Mode> operation (in case of unused RAM address, the second byte is equal to 00H). <Read Device Information> allows access to the ROM area which contains device related information such as the product family, product name, silicon version and register width. The <Global Error Flag> is generated by an OR-combination of all failure events of the device (i.e. bit 0 to bit 6 of the <Global Status Byte>. Table 21. Global status byte Bit Description Polarity Comment 0 Software reset or under/overvoltage Active high Depends on bit 5 of <Global Status Byte>: Bit 5 Bit 0 0 Set if software reset (SDI stuck at 1 or 0) 1 Logical OR of the under- / overvoltage status bits 1 Overcurrent detected Active high Set by any overcurrent event 2 Open-load detected Active high Set by any open-load event 3 Temp warning Active high 4 Thermal shutdown / chip overload Active high 5 Not (chip reset or communication error) Active low Activated by all internal reset events that change device state or configuration registers (e. g. software reset, VCC under-voltage, etc.). The bit is set after a valid communication with any register. This bit is initially ‘0’ and is set to ‘1’ by a valid SPI communication 6 Communication Error Active high Bit is set if the number of clock cycles during CSN = low does not match with the specified frame width or if an invalid bus condition is detected (SDI stuck at 1 or 0). 7 Global Error Flag Active high Logic OR combination of all failures in the <Global Status Byte>. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |