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PCM16C010 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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PCM16C010 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 38 page  30 Pinout Description TABLE 3-1 PC Card Host-Side Pins Pin Pin Pin Level Internal Description Name Type No Compatibility Resistor HDATA(150) IO 39 – 41 43 45 TTL 6 mA l 100k to GND PC Card Host Data Bus 46 66 – 71 73 – 76 HADDR(120) I 47 – 52 54 – 56 TTL l 100k to GND PC Card Host Address Bus 59 60 62 64 HOE I 63 TTL l 100k to VCC PC Card Host uses this pin to read common or attribute memory space HWE I 58 TTL l 100k to VCC PC Card Host uses this pin to write common or attribute memory space HIORD I 79 TTL l 100k to VCC PC Card Host uses this pin to read IO memory space HIOWR I 80 TTL l 100k to VCC PC Card Host uses this pin to write IO memory space IREQ O 57 CMOS 6 mA Interrupt Request signal to PC Card Host HWAIT O 33 CMOS 6 mA This pin allows the PCM16C02 to insert wait states in a PC Card transaction IOIS16 O 42 CMOS 6 mA Low indicates this IO access to the card is capable of 16-bit access The Function may use IOCS16 to control this signal and inform the host if a 16-bit access to the target is feasible INPACK O 34 CMOS 6 mA Signals a valid IO read CE1 I 65 TTL l 100k to VCC Indicates even address byte Odd addresses are not released CE1 and CE2 assertion encodings are specified by the PC Card Standard CE2 I 78 TTL l 100k to VCC Indicates odd addressing only CE1 and CE2 assertion encodings are specified by the PC Card Standard REG I 35 TTL l 100k to VCC Indicates access to attribute memory space or IO address space REG must be high to access common memory space RESET I 32 TTL Schmitt l 100k to VCC Asynchronously resets the PCM16C02 SPKR O 37 CMOS 6 mA If Audio bits are set in the Card Configuration Status Register and in the Function Configuration Status Register then SPKR is invert of SPK IN pin else SPKR is high STSCHG O 38 CMOS 6 mA STSCHG is asserted when the Changed bit and SigChg bit are set in the Card Configuration Status Register http www nationalcom 4 |
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