SCANPSC110 datasheet(8/29 Pages) NSC

8 / 29 page

Overview of SCANPSC110F Bridge

Functions (Continued)

Following

hardware

reset,

the

TAP

controller

state-machine is in the

Test-Logic-Reset (TLR) state; the

’PSC110F-selection

state-machine

the

Wait-For-Address state; and each of the three port-selection

state-machines is in the

Parked-TLR state. The ’PSC110F is

then ready to receive Level-1 protocol, followed by Level-2

protocol.

Tester/SCANPSC110F Bridge

Interface

An IEEE 1149.1 system tester sends instructions to a

’PSC110F via that ’PSC110F’s backplane scan-port. Follow-

ing test logic reset, the ’PSC110F’s selection state-machine

is in the

Wait-For-Address state. When the ’PSC110F’s TAP

controller is sequenced to the Shift-IR state, data shifted in

through the TDI

B input is shifted into the ’PSC110F’s instruc-

tion register. Note that prior to successful selection of a

’PSC110F, data is not shifted out of the instruction register

and out through the ’PSC110F’s TDO

B output, as it is during

normal scan operations. Instead, as each new bit enters the

instruction register’s most-significant bit, data shifted out

from the least-significant bit is discarded.

When the instruction register is updated with the address

data, the ’PSC110F’s address-recognition logic compares

the six least-significant bits of the instruction register with the

6-bit assigned address which is statically present on the

(0–5) inputs. Simultaneously, the scanned-in address is

compared with the reserved Broadcast and Multi-cast ad-

dresses.

address

match

detected,

the

’PSC110F-selection state-machine enters one of the two se-

lected states. If the scanned address does not match a valid

single-slot address or one of the reserved broadcast/

multi-cast addresses, the ’PSC110F-selection state-machine

enters the

Unselected state.

Note that the SLOT inputs

should not be set to a value cor-

responding to

a multi-cast group,ortothe broadcast ad-

dress. Also note that the single-’PSC110F selection process

must be performed for all ’PSC110Fs which are subse-

quently to be addressed in multi-cast mode. This is required

because each such device’s Multi-cast Group Register

(MCGR) must be programmed with a multi-cast group num-

ber, and the MCGR is not accessible to the test controller un-

til

that

’PSC110F

has

first

entered

the

Selected-Single-’PSC110F state.

Once a ’PSC110F has been selected, Level-2 protocol is

used to issue commands and to access the chip’s various

registers.

The SCANPSC110F Bridge includes a number of registers

which are used for ’PSC110F selection and configuration,

scan data manipulation, and scan-support operations. These

registers can be grouped as shown in

Table 3.

The specific fields and functions of each of these registers

are detailed in the section of this document titled “Data Reg-

ister Descriptions”.

Note that when any of these registers is selected for inser-

tion into the ’PSC110F’s scan-chain, scan data enters

through that register’s most-significant bit. Similarly, data

that is shifted out of the register is fed to the scan input of the

next-downstream device in the scan-chain.

TABLE 3. Registers

BSDL Name

Description

Instruction Register

INSTRUCTION

’PSC110F addressing and instruction-decode

IEEE Std. 1149.1 required register

Boundary-Scan Register

BOUNDARY

IEEE Std. 1149.1 required register

Bypass Register

BYPASS

IEEE Std. 1149.1 required register

Device Identification Register

IDCODE

IEEE Std. 1149.1 optional register

Multi-Cast Group Register

MCGR

’PSC110F-group address assignment

Mode Register

MODE

’PSC110F local-port configuration and control bits

Linear-Feedback Shift Register

LFSR

’PSC110F scan-data compaction (signature generation)

TCK Counter Register

CNTR

Local-port TCK clock-gating (for BIST)

Addressing Scheme

The SCANPSC110F Bridge architecture extends the func-

tionality of the IEEE 1149.1 Standard by supplementing that

protocol with an addressing scheme which allows a test con-

troller to communicate with specific ’PSC110Fs within a net-

work of ’PSC110Fs. That network can include both

multi-drop and hierarchical connectivity. In effect, the

’PSC110F architecture allows a test controller to dynamically

select specific portions of such a network for participation in

scan operations. This allows a complex system to be parti-

tioned into smaller blocks for testing purposes.

The ’PSC110F provides two levels of test-network partition-

ing capability. First, a test controller can select entire indi-

vidual ’PSC110Fs, specific sets of ’PSC110Fs (multi-cast

groups),

all

’PSC110Fs

(broadcast).

This

’PSC110F-selection process is supported by a “Level-1”

communication protocol. Second, within each selected

’PSC110F, a test controller can select one or more of the

chip’s three local scan-ports. That is, individual local ports

can be selected for inclusion in the (single) scan-chain which

a ’PSC110F presents to the test controller. This mechanism

allows a controller to select specific terminal scan-chains

within the overall scan network. The port-selection process is

supported by a “Level-2” protocol.

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