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SCANPSC110 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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SCANPSC110 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 29 page  SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) General Description The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advan- tage of a hierarchical approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remain- ing modules. Each SCANPSC110F Bridge supports up to 3 local scan rings which can be accessed individually or com- bined serially. Addressing is accomplished by loading the in- struction register with a value matching that of the Slot in- puts. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simulta- neously tested. Features n True IEEE1149.1 hierarchical and multidrop addressable capability n The 6 slot inputs support up to 59 unique addresses, a Broadcast Address, and 4 Multi-cast Group Addresses n 3 IEEE 1149.1-compatible configurable local scan ports n Mode Register allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three n 32-bit TCK counter n 16-bit LFSR Signature Compactor n Local TAPs can be tri-stated via the OE input to allow an alternate test master to take control of the local TAPs n The IP version of this device supports features not described in this datasheet such as 8 slot inputs for enhanced address capability and additional instructions. For a completed description of the additional instructions supported, refer to the SCANPSC110 supplemental datasheet. Connection Diagrams TRI-STATE® is a registered trademark of National Semiconductor Corporation. 28-Pin CDIP and Flatpak DS100327-1 Pin Assignment for LCC DS100327-2 October 1999 © 1999 National Semiconductor Corporation DS100327 www.national.com |
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