ST7DALIF2 datasheet(108/171 Pages) STMICROELECTRONICS

108 / 171 page

Serial peripheral interface (SPI)

ST7DALIF2

108/171

Figure 51.

Single master / multiple slave configuration

17.5

Low power modes

17.5.1

Using the SPI to wake-up the device from Halt mode

In slave configuration, the SPI is able to wake-up the Device from Halt mode through a SPIF

interrupt. The data received is subsequently read from the SPIDR register when the

software is running (interrupt vector fetch). If multiple data transfers have been performed

before software clears the SPIF bit, then the OVR bit is set by hardware.

Note:

When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to

perform an extra communications cycle to bring the SPI from Halt mode state to normal

state. If the SPI exits from Slave mode, it returns to normal state immediately.

Caution:

The SPI can wake-up the Device from Halt mode only if the Slave Select signal (external SS

pin or the SSI bit in the SPICSR register) is low when the Device enters Halt mode. So if Slave

selection is configured as external (see Section 17.4.1), make sure the master drives a low

level on the SS pin when the slave enters Halt mode.

MISO

MOSI

MISO

SCK

Slave

Device

Slave

Device

Slave

Device

Slave

Device

Master

Device

Table 46.

Effect of low power modes on SPI

Mode

Description

Wait

No effect on SPI.

SPI interrupt events cause the Device to exit from Wait mode.

Halt

SPI registers are frozen.

In Halt mode, the SPI is inactive. SPI operation resumes when the Device is

woken up by an interrupt with “exit from Halt mode” capability. The data received

is subsequently read from the SPIDR register when the software is running

(interrupt vector fetching). If several data are received before the wake-up event,

then an overrun error is generated. This error can be detected after the fetch of

the interrupt routine that woke up the Device.

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