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ST7DALIF2 Datasheet(PDF) 114 Page - STMicroelectronics

Part # ST7DALIF2
Description  Configurable watchdog timer
PDF  171 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7DALIF2 Datasheet(HTML) 114 Page - STMicroelectronics

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10-bit A/D converter (ADC)
ST7DALIF2
114/171
Figure 52.
ADC block diagram
18.3.2
Input voltage amplifier
The input voltage can be amplified by a factor of 8 by enabling the AMPSEL bit in the
ADCDRL register.
When the amplifier is enabled, the input range is 0V to VDD/8.
For example, if VDD = 5V, then the ADC can convert voltages in the range 0V to 430mV with
an ideal resolution of 0.6mV (equivalent to 13-bit resolution with reference to a VSS to VDD
range).
For more details, refer to the Electrical characteristics section.
Note: The amplifier is switched on by the ADON bit in the ADCCSR register, so no
additional startup time is required when the amplifier is selected by the AMPSEL bit.
18.3.3
Digital A/D conversion result
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Electrical
Characteristics Section.
CH2
CH1
EOC SPEED ADON
0
CH0
ADCCSR
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
AINx
ANALOG
MUX
D4
D3
D5
D9
D8
D7
D6
D2
ADCDRH
3
D1
D0
ADCDRL
00
0
AMP
SLOW
AMP
0
RADC
CADC
HOLD CONTROL
x 1 or
x 8
AMPSEL
bit
SEL
fADC
fCPU
0
1
1
0
DIV 2
DIV 4
SLOW
bit
CAL



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