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ST7DALIF2 Datasheet(PDF) 116 Page - STMicroelectronics

Part # ST7DALIF2
Description  Configurable watchdog timer
PDF  171 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7DALIF2 Datasheet(HTML) 116 Page - STMicroelectronics

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10-bit A/D converter (ADC)
ST7DALIF2
116/171
18.6
Interrupts
None.
18.7
Register description
18.7.1
Control/status register (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
It is cleared by hardware when software reads the ADCDRH register or writes to any bit of
the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used together with the SLOW bit to configure the
ADC clock speed. Refer to the table in the SLOW bit description.
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on
Bits 4:3 = Reserved. Must be kept cleared.
Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They select the analog input to convert.
Table 50.
Effect of low power modes on ADC
Mode
Description
Wait
No effect on A/D Converter
Halt
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilization time
tSTAB (see Electrical Characteristics) before accurate conversions can be
performed.
7
0
EOC
SPEED
ADON
0
CH3
CH2
CH1
CH0
Table 51.
Channel selection bits
Channel pin(1)
CH2
CH1
CH0
AIN0
0
0
0
AIN1
0
0
1
AIN2
0
1
0



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