ST7FOXU0 datasheet(65/123 Pages) STMICROELECTRONICS

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ST7FOXU0

On-chip peripherals

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Figure 29.

Lite timer block diagram

10.1.3

Functional description

The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it

starts incrementing from 0 at a frequency of fOSC. A counter overflow event occurs when the

counter rolls over from 1F3Fh to 00h. If fOSC = 8 MHz, then the time period between two

counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the

LTCSR register.

When the timer overflows, the TBF bit is set by hardware and an interrupt request is

generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register.

10.1.4

Watchdog

The watchdog is enabled using the WDGE bit. The normal Watchdog timeout is 2 ms

(@ fosc = 8 MHz), after which it then generates a reset.

To prevent this watchdog reset occurring, software must set the WDGD bit. The WDGD bit is

cleared by hardware after tWDG. This means that software must write to the WDGD bit at

regular intervals to prevent a watchdog reset occurring. Refer to Figure 30.

If the watchdog is not enabled immediately after reset, the first watchdog timeout will be

shorter than 2 ms, because this period is counted starting from reset. Moreover, if a 2 ms

period has already elapsed after the last MCU reset, the watchdog reset will take place as

soon as the WDGE bit is set. For these reasons, it is recommended to enable the Watchdog

immediately after reset.

A Watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced

watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the

WDGRF bit has to be set.

LTCSR

WATCHDOG

13-bit UPCOUNTER

8-bit

fLTIMER

fWDG

8 MSB

LTIC

fOSC

WDGD

WDGE

WDG

TBF

TBIE

ICF

ICIE

WATCHDOG RESET

LTTB INTERRUPT REQUEST

LTIC INTERRUPT REQUEST

LTICR

INPUT CAPTURE

1 or 2 ms

Timebase

(@ 8 MHz

fOSC)

To 12-bit AT TImer

fLTIMER

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