ST7FOXU0 datasheet(50/123 Pages) STMICROELECTRONICS

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Power saving modes

ST7FOXU0

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8.4.1

Active-halt mode

Active-Halt mode is the lowest power consumption mode of the MCU with a real time clock

available. It is entered by executing the ‘HALT’ instruction when active halt mode is enabled.

The MCU can exit Active-Halt mode on reception of a Lite timer/ AT timer interrupt or a

Reset.

●

When exiting Active-Halt mode by means of a Reset, a 256 CPU cycle delay occurs.

After the start up delay, the CPU resumes operation by fetching the Reset vector which

woke it up (see Figure 21).

●

When exiting Active-Halt mode by means of an interrupt, the CPU immediately

resumes operation by servicing the interrupt vector which woke it up (see Figure 21).

When entering Active-Halt mode, the I bit in the CC register is cleared to enable interrupts.

Therefore, if an interrupt is pending, the MCU wakes up immediately.

In Active-Halt mode, only the main oscillator and the selected timer counter (LT/AT) are

running to keep a wake-up time base. All other peripherals are not clocked except those

which get their clock supply from another clock generator (such as external or auxiliary

oscillator).

Caution:

As soon as Active-Halt is enabled, executing a HALT instruction while the Watchdog is

active does not generate a Reset if the WDGHALT bit is reset.

This means that the device cannot spend more than a defined delay in this power saving

mode.

Figure 20.

Active-halt timing overview

This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.

HALT

RUN

256 CPU

CYCLE DELAY 1)

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

[Active Halt Enabled]

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