Copyright

© ANPEC Electronics Corp.

Rev. A.1 - Dec., 2016

APW7252

www.anpec.com.tw

7

Pin Description

P IN

NO.

NAME

Function

A 1

E NN

V N E nable Inpu t. Note, this pin has 200kΩ (typ .) pul l-down to AG ND.

A 2

OUTN

Neg ati ve Char ge Pump Ou tp ut. Con nect a 4.7

µF capacitor to ground. Connecting two 4.7µF capacitors

to grou nd will lower th e nega tive ch arge pu mp output vol tag e r ipple.

A 3

CFLY 2

Cha rge Pump Neg ative Con necti on. Pl ace a capa citor be tween CFLY1 and CFLY 2 to ge nerate the

O UTN vo lta ge.

B 1

ENP

REG a nd OUTP Enab le Inp ut. Note , this pi n has 2 00kΩ(typ.) p ull-do wn to A GND.

B 2

S CL

S erial Clock Con nection fo r I

2

C In ter face .

B3 , E1

PG ND

P ower groun d.

C1

V IN

Inpu t Su pply. Co nnect a 4.7

µF to ground.

C2

SDA

S erial Data Co nnection for I

2

C Inte rfa ce .

C3

CFLY 1

Cha rge Pump P ositive Conn ection . Pla ce a capacitor between CFLY 1 a nd CFLY2 to cr eate the O UTN

voltage .

D1

SW

S witch node for boost conver ter. Conn ect an indu ctor between the VIN and SW pins fo r bo ost converter

o peration .

D2

AG ND

A nalog g round .

D3,E2

REG

B oost Converter O utput. Th e boost converter ou tp ut supp lies the po wer to the nega tive charg e pump

a nd LDO. Co nnect a 4.7

µF capacitor to ground.

E 3

O UTP

L DO O utput. Conn ect a 4.7

µF capacitor to ground.