REV. 0

ADF7010

–17–

VOLTAGE CONTROLLED OSCILLATOR (VCO)

An on-chip VCO is included on the transmitter. The VCO

converts the control voltage generated by the loop filter into an

output frequency that is sent to the antenna via the power

amplifier (PA). The VCO has a typical gain of 80 MHz/V and

operates from 900 MHz–940 MHz. The PD1 bit in the function

register is the active high bit that turns on the VCO. A frequency

divide by 2 is included to allow operation in the lower 450 MHz

band. To enable operation in the lower band, the V1 bit in the

N Register should be set to 1.

The VCO needs an external 220 nF between the VCO and the

regulator to reduce internal noise.

MUX

VCO SELECT BIT

TO PA AND

N DIVIDER

DIVIDE

BY 2

VCO CONTROL BIT

LOOP FILTER

220nF

VCO

Figure 7. Voltage Controlled Oscillator

RF OUTPUT STAGE

The RF output stage consists of a DAC with a number of current

sources to adjust the output power level. To set up the power level:

FSK GFSK: The output power is set using the modulation

register by entering a 7-bit number into the bits P1–P7. The two

MSBs set the range of the output stage, while the five LSBs set

the output power in the selected range.

ASK: The output power as set up for FSK is the output power

for a TxDATA of 1. The output power for a zero data bit is set

up the same way but using the bits D1–D7.

The output stage is powered down by setting bit PD2 in the

Function register to zero.

P5

P1

P7, P6

HIGH

MED

LOW

Figure 8. Output Stage

SERIAL INTERFACE

The serial interface allows the user to program the four 24-bit

registers using a 3-wire interface. (CLK, Data, and Load Enable).

The serial interface consists of a level shifter, 24-bit shift register,

and four latches. Signals should be CMOS compatible. The serial

interface is powered by the regulator, and therefore is inactive

when CE is low.

Table I. C2, C1 Truth Table

C2

C1

Data Latch

00

R Register

01

N Register

10

Modulation Register

11

Function Register

Data is clocked into the shift register, MSB first, on the rising edge

of each clock (CLK). Data is transferred to one of four latches on

the rising edge of LE. The destination latch is determined by the

value of the two control bits (C2 and C1). These are the two

LSBs, DB1 and DB0, as shown in the timing diagram of Figure 1.

PA

L1

C1

50

L2

Figure 9. Output Stage Matching