signals are referenced to GND which is the common of GNDA and GNDD (Continued)

TIMING SPECIFICATIONS

(Continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

DIGITAL INTERFACE TIMING

BCLK Frequency

4096

41

MHz

Clock Pulse Width High

70

ns

and Low for BCLK

70

Rise Time and Fall Time

15

ns

of BCLK

15

BCLK Transition to MCLK High or Low

b

30

30

ns

Set up Time FS Valid to BCLK Invalid

20

4ns

Hold Time BCLK Low to FS Invalid

40

30

ns

Setup Time BI Valid to BCLK Invalid

30

11

ns

Hold Time BCLK Valid to BI Invalid

40

7ns

Setup Time DI Valid to BCLK Low

30

ns

Hold Time BCLK Low to DI Invalid

40

ns

Delay Time BCLK High to BO Valid

80

ns

Delay Time BCLK Low to BO High-Z

80

120

ns

Delay Time BCLK High to DO valid

80

ns

Delay Time BCLK Low to DO High

40

120

ns

Impedance

Delay Time BCLK High to TSB Low

120

ns

Disable Time BCLK Low to TSB High-Z

120

ns

MICROWIRE CONTROL INTERFACE TIMING

Frequency of CCLK

21

MHz

Period of CCLK High

150

ns

Period of CCLK Low

150

ns

Setup Time CS Low to CCLK High

50

ns

Hold Time CCLK High to CS Transition

40

ns

Setup Time CI Valid to CCLK High

50

ns

Hold Time CCLK High to CI Invalid

20

ns

Delay Time CCLK Low to CO Valid

80

ns

Delay Time CS High to CO High-Z

80

ns

Delay Time CCLK to INT High-Z

100

ns

Notes

For the purposes of this specification the following conditions apply

b Delay times are measured from the input signal Valid to the output signal Valid

c Setup times are measured from the Data input Valid to the clock input Invalid

d Hold times are measured from the clock signal Valid to the Data input Invalid

3