LINE CONTROL REGISTERS CTRLN

Each of the 4 transceivers has a Line Control Register

CTRL0 – CTRL3 which provides for control of loop activa-

tion Ioopbacks Interrupt enabling and D channel interface

enabling Table 3 lists the functions

POWER ON INITIALIZATION

Following the initial application of power the QDASL enters

the power-down (de-activated) state in which all the internal

circuits are inactive and in a low power state except for a

Line-Signal Detect Circuit for each of the 4 lines and the

necessary bias circuits The 4 line outputs Lo0 – Lo3 are in

a high impedance state and all digital outputs are inactive

All bits in the Line Control Registers power-up initially set to

‘‘0’’ While powered-down each Line-Signal Detect Circuit

continually monitors its line to detect if the far-end initiates

loop transmission

POWER-UPDOWN CONTROL

To power-up the device and initiate activation bit C7 in any

of the 4 Line Control Registers must be set high see Table

III Setting C7 low de-activates the loop or puts the channel

in power-down state During power-down state internal reg-

ister data is retained and still can be accessed

LOOPBACKS

Four different loopbacks can be set for each line They are

enabled and disabled by setting the corresponding bits in

the Control Register see Table III In addition a line must

be activated to see the effect of loopback commands

When bit 5 is set to 1 this loop will transfer all three

channels B1 B2 and D that are received at the Li pin

back to the Lo pin Data out on BODO is still the same

as received at the Li input

2 B1 Line Loopback

When bit 4 is set high the loop path is the same as (1)

but only data on the B1 channel is looped back to the

line Transmit data in the B2 and D channels is from the

BiDI pins

3 B2 Line Loopback

As (2) but for the B2 channel

back to BODO The data is also transmitted to the line

TIME-SLOT ASSIGNMENT

The digital interface of the QDASL uses time-division multi-

plexing with data framed in up to 64 possible 8-bit time-

slots per 125 ms frame Channels B1 and B2 for all 4 lines

are clocked in (towards the line) at the BI pin and clocked

out (from the line) at the BO pin A separate port is provided

for the D channel data for all 4 lines which is clocked in on

DI and out on DO In addition to time-slot assignment D

channel data may be assigned into 2-bit sub-slots within

each time slot with up to 256 sub-slots per frame (with

tive edge of BCLK after the FS signal goes high and count-

ing of timeslots starts from zero at the beginning of the

frame

Figure 4 shows the timing with some example time-

slot assignments

For each of the 4 QDASL lines there are 6 Time-Slot As-

signment control registers one each for transmit and re-

ceive B1 B2 and D channels Selection of time-slots for

transmit data into the BI or DI pin is made by writing the

timeslot number (in Hex notation) into the appropriate TSX

register TSXB1 is the time-slot assignment for the transmit

B1 TSXB2 is the time-slot assignment register for the trans-

mit B2 channel and TSXD is the sub-slot assignment regis-

ter for the transmit D channel

TABLE III Byte 2 of Control Register (CTRLN)

Bit Number

Function

76543210

0

Deactivate Line

1

Activate Line

0

Disable Digital Loopback

1

0

Disable Line Loopback

1

0

Disable B1 Line Loopback

1

Enable B1 Line Loopback

0

Disable B2 Line Loopback

1

Enable B2 Line Loopback

0

Disable Interrupt from this Line

1

Enable Interrupt from this Line

0

D Channel enabled from DO to Line

1

D Channel disabled from DO to Line

0

D Channel enabled from Line to DI

1

D Channel disabled from Line to DI

8