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USBN9602 Datasheet(PDF) 39 Page - National Semiconductor (TI) |
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USBN9602 Datasheet(HTML) 39 Page - National Semiconductor (TI) |
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39 / 45 page ![]() 39 www.national.com 14.0 Electrical Characteristics (Continued) 14.1 Parallel Interface Timing (MODE[1:0] = 00b) INTERFACE TIMING (MODE = 0) (4.5V< VCC < 5.5V, 0°C < TA< +70°C, unless otherwise specified) Symbol Parameter Condition Min Typ Max Units tCS Chip Select Setup Time CL 50pF 0 nS tCH Chip Select Hold Time CL 50pF 5 nS tAS Address Setup Time CL 50pF 0 nS tAH Address Hold Time CL 50pF 0 nS tRW Read Pulse Width 1 1. Clock Input: CKI = 48MHz on this device. CL 50pF 1/CKI nS tRC Read Cycle Time 2, 3 2. Memory Clock: MCLK = CKI/4 = 12 MHz. 3. Time until next Read or Write occurs. CL 50pF 3/MCLK nS tRDV Data output Valid after Read Low CL 50pF 20 30 nS tRDZ Data output Hold after Read High CL 50pF 0 8 nS tWW Write Pulse Width 1 CL 50pF 1/CKI nS tWC Write Cycle Time 2,3 CL 50pF 3/MCLK nS tDS Data input Setup Time CL 50pF 25 nS tDH Data input Hold Time CL 50pF 5 nS |
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