USBN9602 datasheet(13/45 Pages) NSC

13 / 45 page

www.national.com

8.0 MICROWIRE/PLUS Interface

The MICROWIRE/PLUS interface allows the USBN9602

to function as a peripheral of a CPU or microcontroller via

a serial interface. This mode is selected by pulling the

MODE1 pin high and the MODE0 pin low. The MICROW-

IRE/PLUS mode uses pins called chip select (CS), serial

clock (SK), serial data in (SI), and serial data out (SO), as

shown in Figure 10.

The MICROWIRE interface is enabled by a falling edge of

CS and reset with a rising edge of CS. Data on SI is shift-

ed in after the rising edge of SK and data is shifted out on

SO after the falling edge of SK. Data transfer from and to

the shift register is done after the falling edge of the eighth

SK clock. Data is transferred with the most significant bit

first. Table 1 summarizes the available commands for the

MICROWIRE interface.

Note: A write operation to any register always reads out the contents of the

read does not clear the bit in the respective register, even for a clear-on-read

(“Cor”) type bit. An exception is writing to the TXDx (transmit data) registers,

which causes undefined data to be read out during the next cycle.

0x00

0x3F

DATA_IN

DATA OUT

DATA IN

DATA_OUT

ADDR

ADDRESS

Figure 10. MICROWIRE Interface Block Diagram

SHIFT REG

CMD[1:0]

SYNC

USBN9602 Datasheet(PDF) 13 Page - National Semiconductor (TI)