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AS4C4M16S Datasheet(PDF) 13 Page - Alliance Semiconductor Corporation |
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AS4C4M16S Datasheet(HTML) 13 Page - Alliance Semiconductor Corporation |
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13 / 53 page ![]() A8 A7 Test Mode 0 0 Normal 1 0 Vendor Use Only 0 1 Vendor Use Only A3 Burst Type 0 Sequential 1 Interleave A2 A1 A0 Burst Length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 1 1 Full Page (Sequential) All other Reserved FEBRUARY 2011 AS4C4M16S Table 5. Mode Register Bitmap BA0,1 A11,A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RFU* RFU* WBL Test Mode CAS# Latency BT Burst Length A9 Write Burst Length 0 Burst 1 Single Bit A6 A5 A4 CAS# Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 0 1 Reserved All other Reserved *Note: RFU (Reserved for future use) should stay “0” during MRS cycle. CLK CKE CS# T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 tMRD RAS# CAS# WE# BA0,1 A10 A0-A9, A11 Address Key DQM DQ Hi-Z tRP PrechargeAll Mode Register Set Command Any Command Don’t Care Figure 15. Mode Register Set Cycle 12 Rev2.0 May 2014 |
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