AS6C1616A datasheet(9/12 Pages) ALSC

Part #	AS6C1616A

Description	Low Data Retention Voltage

PDF	12 Pages

Scroll/Zoom	100%

Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

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9 / 12 page

TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS1, a high CS2 and low WE. A write begins at the latest transition among CS1

goes low, CS2 goes high and WE goes low. A write ends at the earliest transition among CS1 goes high, CS2 goes low and WE

goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS1 going low or CS2 going high to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high or CS2

going low.

tWC

Address

CS1

CS2

UB,LB

Data in

Data out

tCW1,2(2)

tWR(4)

tAW

tBW

tWP(1)

tDW

tDH

High-Z

Data Valid

tAS(3)

AUGUST 2010

1024K X 16 BIT LOW POWER CMOS SRAM

AS6C1616A

AS6C1616A Datasheet(PDF) 9 Page - Alliance Semiconductor Corporation