LMH6550 datasheet(15/17 Pages) NSC

15 / 17 page

Application Section (Continued)

CAPACITIVE DRIVE

As noted in the Driving ADC section, capacitive loads should

be isolated from the amplifier output with small valued resis-

tors. This is particularly the case when the load has a resis-

tive component that is 500

Ω or higher. A typical ADC has

capacitive components of around 10 pF and the resistive

component could be 1000

Ω or higher. If driving a transmis-

sion line, such as 50

Ω coaxial or 100Ω twisted pair, using

matching resistors will be sufficient to isolate any subse-

quent capacitance. For other applications see the “Sug-

gested Rout vs. Cap Load” charts in the Typical Perfor-

mance Characteristics section.

POWER DISSIPATION

The LMH6550 is optimized for maximum speed and perfor-

mance in the small form factor of the standard SOIC pack-

age, and is essentially a dual channel amplifier. To ensure

maximum output drive and highest performance, thermal

shutdown is not provided. Therefore, it is of utmost impor-

tance to make sure that the T

JMAX is never exceeded due to

the overall power dissipation.

Follow these steps to determine the Maximum power dissi-

pation for the LMH6550:

Calculate the quiescent (no-load) power: P

AMP =ICC*

S), where VS =V

+ -V−. (Be sure to include any current

through the feedback network if V

OCM is not mid rail.)

Calculate the RMS power dissipated in each of the

output stages: P

D (rms) = rms ((VS -V

OUT)*I

OUT)+

rms ((V

S −V

−

OUT)*I

−

OUT) , where VOUT and IOUT are

the voltage and the current measured at the output pins

of the differential amplifier as if they were single ended

amplifiers and V

S is the total supply voltage.

Calculate the total RMS power: P

T =PAMP +PD.

The maximum power that the LMH6550 package can dissi-

pate at a given temperature can be derived with the following

equation:

MAX = (150˚ – TAMB)/

JA, where TAMB = Ambient tempera-

ture (˚C) and

JA = Thermal resistance, from junction to

ambient, for a given package (˚C/W). For the SOIC package

JA is 150˚C/W.

NOTE: If V

CM is not 0V then there will be quiescent current

flowing in the feedback network. This current should be

included in the thermal calculations and added into the qui-

escent power dissipation of the amplifier.

ESD PROTECTION

The LMH6550 is protected against electrostatic discharge

(ESD) on all pins. The LMH6550 will survive 2000V Human

Body model and 200V Machine model events. Under normal

operation the ESD diodes have no effect on circuit perfor-

mance. There are occasions, however, when the ESD di-

odes will be evident. If the LMH6550 is driven by a large

signal while the device is powered down the ESD diodes will

conduct . The current that flows through the ESD diodes will

either exit the chip through the supply pins or will flow

through the device, hence it is possible to power up a chip

with a large signal applied to the input pins. Using the

shutdown mode is one way to conserve power and still

prevent unexpected operation.

BOARD LAYOUT

The LMH6550 is a very high performance amplifier. In order

to get maximum benefit from the differential circuit architec-

ture board layout and component selection is very critical.

The circuit board should have low a inductance ground plane

and well bypassed broad supply lines. External components

should be leadless surface mount types. The feedback net-

work and output matching resistors should be composed of

short traces and precision resistors (0.1%). The output

matching resistors should be placed within 3-4 mm of the

amplifier as should the supply bypass capacitors. The

LMH730154 evaluation board is an example of good layout

techniques. Evaluation boards are available free of charge

through the product folder on National’s web site.

The LMH6550 is sensitive to parasitic capacitances on the

amplifier inputs and to a lesser extent on the outputs as well.

Ground and power plane metal should be removed from

beneath the amplifier and from beneath R

F and RG.

With any differential signal path symmetry is very important.

Even small amounts of assymetery will contribute to distor-

tion and balance errors.

20130106

FIGURE 11. Transformer Out Low Impedance Load

20130103

FIGURE 12. Driving 50

Ω Test Equipment

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