STR71XFXX datasheet(17/80 Pages) STMICROELECTRONICS

17 / 80 page

STR71xFxx STR710RZ

System architecture

Doc ID 10350 Rev 13

17/80

V33IO-PLL

Supply voltage for digital I/O circuitry and for PLL

reference

N.C.

Not connected (not bonded)

VSSIO-PLL

Ground voltage for digital I/O circuitry and for PLL

reference4)

N.C.

Not connected (not bonded)

DBGRQS

Debug Mode request input (active high)

CKOUT

8mA

Clock output (fPCLK2) Note: Enabled by CKDIS

Reference clock input

P0.15/

WAKEUP

ITT XX

Port 0.15

Wakeup from Standby mode input.

Note: This port is input only.

N.C.

Not connected (not bonded)

RTCXTI

Realtime Clock input and input of 32 kHz

oscillator amplifier circuit

RTCXTO

Output of 32 kHz oscillator amplifier circuit

STDBY

I/O

4mA

Input: Hardware Standby mode entry input active

low. Caution: External pull-up to V33 required to

select normal mode.

Output: Standby mode active low output following

Software Standby mode entry.

Note: In Standby mode all pins are in high

impedance except those marked Active in Stdby

RSTIN

ICT

X Reset input

N.C.

Not connected (not bonded)

VSSBKP

X Stabilization for low power voltage regulator.

V18BKP

Stabilization for low power voltage regulator.

Requires external capacitors of at least 1µF

between V18BKP and VSS18BKP. See Figure 5.

Note: If the low power voltage regulator is

bypassed, this pin can be connected to an

external 1.8V supply.

N.C.

Not connected (not bonded)

N.C.

Not connected (not bonded)

V18

Stabilization for main voltage regulator. Requires

external capacitors of at least 10µF + 33nF

between V18 and VSS18. See Figure 5.

Table 4.

STR710 pin description

Pin n°

Pin name

Input

Output

Main

function

(after

reset)

Alternate function

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