SC16C750B datasheet(13/44 Pages) PHILIPS

13 / 44 page

Philips Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Product data

Rev. 03 — 13 December 2004

13 of 44

9397 750 14453

6.6 DMA operation

The SC16C750B FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. The user can optionally operate the transmit and receive FIFOs in

the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY

output pins. Tables 6 and 7 show this.

Table 5:

Baud rates using 1.8432 MHz or 3.072 MHz crystal

Using 1.8432 MHz crystal

Using 3.072 MHz crystal

Desired

baud rate

Divisor for

× clock

Baud rate

error

Desired

baud rate

Divisor for

× clock

Baud rate

error

2304

3840

1536

2560

110

1047

0.026

110

1745

0.026

134.5

857

0.058

134.5

1428

0.034

150

768

150

1280

300

384

300

640

600

192

600

320

1200

160

1800

107

0.312

2000

0.69

2000

2400

3600

0.628

4800

7200

1.23

9600

19200

38400

56000

2.86

Table 6:

Effect of DMA mode on state of RXRDY pin

Non-DMA mode

DMA mode

1 = FIFO empty

0-to-1 transition when FIFO empties

0 = at least 1 byte in FIFO

1-to-0 transition when FIFO reaches trigger level,

or time-out occurs

Table 7:

Effect of DMA mode on state of TXRDY pin

Non-DMA mode

DMA mode

1 = at least 1 byte in FIFO

0-to-1 transition when FIFO becomes full

0 = FIFO empty

1-to-0 transition when FIFO becomes empty

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