X76F100P datasheet(2/16 Pages) XICOR

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X76F100

Characteristics subject to change without notice.

2 of 16

REV 1.0 6/22/00

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PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of

the device.

Serial Data (SDA)

SDA is an open drain serial data input/output pin. Dur-

ing a read cycle, data is shifted out on this pin. During

a write cycle, data is shifted in on this pin. In all other

cases, this pin is in a high impedance state.

Chip Select (CS)

When CS is high, the X76F100 is deselected and the

SDA pin is at high impedance and unless an internal

write operation is underway, the X76F100 will be in

standby mode. CS low enables the X76F100, placing it

in the active mode.

Reset (RST)

RST is a device reset pin. When RST is pulsed high

while CS is low the X76F100 will output 32 bits of ﬁxed

data which conforms to the standard for “synchronous

response to reset”. CS must remain LOW and the part

must not be in a write cycle for the response to reset to

occur. See Figure 7. If at any time during the response

to reset CS goes HIGH, the response to reset will be

aborted and the part will return to the standby state.

The response to reset is “mask programmable” only!

DEVICE OPERATION

The X76F100 memory array consists of fourteen

8-byte sectors. Read or write access to the array

always begins at the ﬁrst address of the sector. Read

operations then can continue indeﬁnitely. Write opera-

tions must total 8-bytes.

There are two primary modes of operation for the

X76F100; Protected READ and protected WRITE. Pro-

tected operations must be performed with one of two 8-

byte passwords.

The basic method of communication for the device is

established by ﬁrst enabling the device (CS LOW),

generating a start condition, then transmitting a com-

mand, followed by the correct password. All parts will

be shipped from the factory with all passwords equal to

‘0’. The user must perform ACK Polling to determine

the validity of the password, before starting a data

transfer (see Acknowledge Polling.) Only after the cor-

rect password is accepted and a ACK polling has been

performed, can the data transfer occur.

To ensure the correct communication, RST must

remain LOW under all conditions except when running

a “Response to Reset sequence”.

Data is transferred in 8-bit segments, with each trans-

fer being followed by an ACK, generated by the receiv-

ing device.

If the X76F100 is in a nonvolatile write cycle a “no

ACK” (SDA=High) response will be issued in response

to loading of the command byte. If a stop is issued prior

to the nonvolatile write cycle the write operation will be

terminated and the part will reset and enter into a

standby mode.

The basic sequence is illustrated in Figure 1.

PIN NAMES

PIN CONFIGURATION

Symbol

Description

Chip Select Input

SDA

Serial Data Input/Output

SCL

Serial Clock Input

RST

Reset Input

VCC

Supply Voltage

VSS

Ground

No Connect

SDA

VCC

RST

SCL

VCC

RST

SCL

VSS

SDA

Smart Card

GND

SDA

VCC

RST

SCL

VSS

RST

SCL

SDA

VSS

VCC

PDIP

SOIC

MSOP

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