AM29LV017D datasheet(14/45 Pages) AMD

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Am29LV017D

Figure 2.

Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 8 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during VCC power-up and

power-down transitions, or from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until VCC

is greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#

= VIL, CE# = VIH or WE# = VIH. To initiate a write cy-

cle, CE# and WE# must be a logical zero while OE#

is a logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power

up, the device does not accept commands on the

rising edge of WE#. The internal state machine is

automat ic ally res e t t o reading array da ta on

power-up.

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

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