REV. 0

ADV7183

–27–

Table XX. Status Register

Bit Description

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Register Setting

STATUS[7:0]

2

0

1

Color Kill Active

0

1

White Peak Active

0

1

ADC Overflow Detected

0

1

ADC Underflow Detected

0

1

50 Hz Field Rate Auto Detected

0

1

0

1

Lost Lock (since last read)

0

1

In Lock (current)

NOTES

Table XXI. Info Register

Bit Description

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Register Setting

IDENT[7:0]

2

XXXXXXXX

0 = v85a, 3 = v85b, 4 = v85b3, 5 = v85b3

NOTES

Table XXII. Analog Control Internal Register (Subaddress 13)

Bit Description

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Register Setting

TIM_OE

*

0

Dependent on

OE andTOD

1

HS,VS, F Forced Active

RESERVED

010001

1

Set at Default Value

*Timing Signals Output. Enables the user to force the output drivers for H-SYNC,V-SYNC, and Field into an active state regardless of the OE pin and TOD bit.

Table XXIII. Analog Clamp Control Register (Subaddress 14)

Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

FICL[1:0]

1

0

0

I On for 16 Clock Cycles

0

1

I On for 32 Clock Cycles

1

0

I On for 64 Clock Cycles

1

1

I On for 128 Clock Cycles

FACL[1:0]

2

0

0

I On for 16 Clock Cycles

0

1

I On for 32 Clock Cycles

1

0

I On for 64 Clock Cycles

1

1

I On for 128 Clock Cycles

CCLEN

3

0

I Sources Switched Off

1

I Sources Enabled

VCLEN

4

0

Voltage Clamp Disabled

1

Voltage Clamp Enabled

RESERVED

0

0

Set to Zero

NOTES