CD54HC354 datasheet(9/14 Pages) TI

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Propagation Delay,

→ Y, Y

tPLH, tPHL

CL = 50pF

4.5

CL = 15pF

Propagation Delay,

→ Y, Y

tPLH, tPHL

CL = 50pF

4.5

CL = 15pF

Output Disabling Time,

OEn to Y, Y

tPLZ, tPHZ

CL = 50pF

4.5

CL = 15pF

13, 16

Output Disabling Time,

OE3 to Y, Y

tPLZ, tPHZ

CL = 50pF

4.5

CL = 15pF

13, 16

Output Enabling Time,

OEn to Y, Y

tPZL, tPZH

CL = 50pF

4.5

CL = 15pF

Output Enabling Time,

OE3 to Y, Y

tPZL, tPZH

CL = 50pF

4.5

CL = 15pF

Output Transition Time

tTLH, tTHL

CL = 50pF

4.5

Input Capacitance

CIN

Three-State Capacitance

Power Dissipation

Capacitance

(Notes 4, 5)

CPD

NOTES:

4. CPD is used to determine the dynamic power consumption, per device.

5. PD = VCC

2 (C

PD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

VCC (V)

25oC

-40oC TO 85oC

-55oC TO

125oC

UNITS

TYP

MAX

Test Circuits and Waveforms

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

CLOCK

90%

50%

10%

GND

VCC

trCL

tfCL

50%

tWL

tWH

10%

tWL + tWH =

fCL

CLOCK

2.7V

1.3V

0.3V

GND

trCL = 6ns

tfCL = 6ns

1.3V

tWL

tWH

0.3V

tWL + tWH =

fCL

CD54HC354, CD74HC354, CD74HCT354

CD54HC354 Datasheet(PDF) 9 Page - Texas Instruments

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