COP880C datasheet(12/31 Pages) NSC

12 / 31 page

Functional Description (Continued)

B is the 8-bit address register, can be auto incremented or

decremented.

X is the 8-bit alternate address register, can be incremented

or decremented.

SP is the 8-bit stack pointer, points to subroutine stack (in

RAM).

B, X and SP registers are mapped into the on chip RAM. The

B and X registers are used to address the on chip RAM. The

SP register is used to address the stack in RAM during

subroutine calls and returns.

PROGRAM MEMORY

Program memory consists of 4096 bytes of ROM. These

bytes may hold program instructions or constant data. The

program memory is addressed by the 15-bit program

counter (PC). ROM can be indirectly read by the LAID in-

struction for table lookup.

DATA MEMORY

The data memory address space includes on chip RAM, I/O

and registers. Data memory is addressed directly by the

instruction or indirectly by the B, X and SP registers.

The device has 128 bytes of RAM. Sixteen bytes of RAM are

mapped as “registers” that can be loaded immediately, dec-

remented or tested. Three specific registers: B, X and SP are

mapped into this space, the other bytes are available for

general usage.

The instruction set permits any bit in memory to be set, reset

or tested. All I/O and registers (except the A & PC) are

memory mapped; therefore, I/O bits and register bits can be

directly and individually set, reset and tested. A is not

memory mapped, but bit operations can be still performed on

it.

Note: RAM contents are undefined upon power-up.

RESET

The RESET input when pulled low initializes the microcon-

troller. Initialization will occur whenever the RESET input is

pulled low. Upon initialization, the ports L, G and C are

placed in the TRI-STATE mode and the Port D is set high.

The PC, PSW and CNTRL registers are cleared. The data

and configuration registers for Ports L, G and C are cleared.

The external RC network shown in

Figure 4 should be used

to ensure that the RESET pin is held low until the power

supply to the chip stabilizes.

OSCILLATOR CIRCUITS

Figure 5 shows the three clock oscillator configurations.

A. CRYSTAL OSCILLATOR

The device can be driven by a crystal clock. The crystal

network is connected between the pins CKI and CKO.

Table 1 shows the component values required for various

standard crystal values.

B. EXTERNAL OSCILLATOR

CKI can be driven by an external clock signal. CKO is

available as a general purpose input and/or HALT restart

control.

C. R/C OSCILLATOR

CKI is configured as a single pin RC controlled Schmitt

trigger oscillator. CKO is available as a general purpose

input and/or HALT restart control.

Table 2 shows the variation in the oscillator frequencies as

functions of the component (R and C) values.

OSCILLATOR MASK OPTIONS

The device can be driven by clock inputs between DC and

10 MHz.

TABLE 1. Crystal Oscillator Configuration, T

A = 25˚C

CKI Freq

Conditions

Ω)(MΩ)

(pF)

(MHz)

30–36

CC =5V

30–36

CC = 2.5V

5.6

200

100–150

0.455

CC =5V

DS010802-6

≥ 5X Power Supply Rise Time

FIGURE 4. Recommended Reset Circuit

DS010802-7

FIGURE 5. Crystal and R-C Connection Diagrams

COP880C Datasheet(PDF) 12 Page - National Semiconductor (TI)

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