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FS6209 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part # FS6209
Description  DUAL PLL VCXO CLOCK GENERATOR IC
PDF  6 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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FS6209 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

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February 1999
4
2.4.99
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Table 5: DC Electrical Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
IDD
fXTAL = 13.5MHz; CL = 10pF
20
mA
Voltage Controlled Crystal Oscillator
Crystal Resonator Frequency
fXTAL
Fundamental Mode
5.
13.5
18
MHz
Crystal Loading Capacitance
CL(xtal)
As seen by a crystal connected to XIN and
XOUT (@ VXTUNE = 1.65V)
20
pF
Crystal Resonator Motional Capacitance
C1(xtal)
AT cut
25
fF
VCXO Tuning Range
fXTAL = 13.5MHz; CL = 20pF; CMOT = 25fF
300
ppm
VCXO Tuning Characteristic
Note: positive
-F for positive -V
100
ppm/V
Crystal Drive Level
RXTAL=20 ohm; CL = 20pF
200
uW
Clock Outputs (CLKA, CLKB, CLKC)
High-Level Output Source Current *
IOH
VO = 2.0V
40
mA
Low-Level Output Sink Current *
IOL
VO = 0.4V
17
mA
zOH
VO = 0.1VDD; output driving high
25
Output Impedance *
zOL
VO = 0.1VDD; output driving low
25
Ω
Short Circuit Source Current *
IOSH
VO = 0V; shorted for 30s, max.
55
mA
Short Circuit Sink Current *
IOSL
VO = 3.3V; shorted for 30s, max.
55
mA
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX.
UNITS
Clock Outputs (CLKx)
Duty Cycle *
thi / tclk; Measured at VDD/2
43
57
%
Jitter, Absolute Period (pk-pk) *
tj(∆P)
From rising edge to next rising edge at
VDD/2, CL = 10pF
300
ps
Jitter, RMS Long Term (
σ
y(
τ)) *
tj(LT)
From 0-500
µs at V
DD/2, CL = 10pF
compared to ideal clock source
150
ps
Rise Time *
tr
VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF
1
ns
Fall Time *
tf
VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF
1
ns
Output Frequency Synthesis Error
(unless otherwise noted in Frequency Table)
0
ppm
VCXO Stabilization Time *
tVCXOSTB
From power valid
10
ms
PLL Stabilization Time *
tPLLSTB
From VCXO stable
500
us



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