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HD404848FS Datasheet(PDF) 39 Page - Hitachi Semiconductor |
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HD404848FS Datasheet(HTML) 39 Page - Hitachi Semiconductor |
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39 / 125 page ![]() HD404849 Series 39 In figure 24, the level of the INT 0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge will not be detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge will not be detected in this case either. When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT 0 longer than the interrupt frame. High Low INT Sampling 0 Low Figure 23 Edge Detection A: Low B: Low INT Interrupt frame 0 A: High B: High INT Interrupt frame 0 a. High level period b. Low level period Figure 24 Sampling Example |
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