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LT1976

1976f

PI FU CTIO S

CSS (Pin 9): A capacitor from the CSS pin to the regulated

output voltage determines the output voltage ramp rate

during start-up. When the current through the CSS capaci-

tor exceeds the CSS threshold (ICSS), the voltage ramp of

the output is limited. The CSS threshold is proportional to

the FB voltage (see Typical Performance Characteristics)

and is defeated for FB voltage greater than 0.9V (typical).

See Soft-Start section in Applications Information for

details.

BIAS (Pin 10): The BIAS pin is used to improve efficiency

when operating at higher input voltages and light load

current. Connecting this pin to the regulated output volt-

age forces most of the internal circuitry to draw its

operating current from the output voltage rather than the

input supply. This architecture increases efficiency espe-

cially when the input voltage is much higher than the

output. Minimum output voltage setting for this mode of

operation is 3V.

VC (Pin 11): The VC pin is the output of the error amplifier

and the input of the peak switch current comparator. It is

normally used for frequency compensation, but can also

serve as a current clamp or control loop override. VC sits

at about 0.45V for light loads and 2.2V at maximum load.

During the sleep portion of Burst Mode operation, the VC

pin is held at a voltage slightly below the burst threshold

for better transient response. Driving the VC pin to ground

will disable switching and place the IC into sleep mode.

FB (Pin 12): The feedback pin is used to determine the

output voltage using an external voltage divider from the

output that generates 1.25V at the FB pin . When the FB pin

drops below 0.9V, switching frequency is reduced, the

SYNC function is disabled and output ramp rate control is

enabled via the CSS pin. See the Feedback section in

Applications Information for details.

PGFB (PIN 13): The PGFB pin is the positive input to a

comparator whose negative input is set at VPGFB. When

PGFB is taken above VPGFB, current (ICSS) is sourced into

the CT pin starting the PG delay period. When the voltage

on the PGFB pin drops below VPGFB, the CT pin is rapidly

discharged resetting the PG delay period. The PGFB volt-

age is typically generated by a resistive divider from the

regulated output or input supply. See Power Good section

in Applications Information for details.

SYNC (Pin 14): The SYNC pin is used to synchronize the

internal oscillator to an external signal. It is directly logic

compatible and can be driven with any signal between

20% and 80% duty cycle. The synchronizing range is

equal to maximum initial operating frequency up to 700kHz.

When the voltage on the FB pin is below 0.9V the SYNC

function is disabled. See the Synchronizing section in

Applications Information for details.

SHDN (Pin 15): The SHDN pin is used to turn off the

regulator and to reduce input current to less than 1

µA. The

SHDN pin requires a voltage above 1.2V with a typical

source current of 3

µA to take the IC out of the shutdown

state.

PG (Pin 16): The PG pin is functional only when the SHDN

pin is above its threshold, and is active low when the

internal clamp on the CT pin is below its clamp level and

high impedance when the clamp is active. The PG pin has

a typical sink capability of 200

µA. See the Power Good

section in Applications Information for details.

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