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HT9B95 Datasheet(PDF) 14 Page - Holtek Semiconductor Inc |
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HT9B95 Datasheet(HTML) 14 Page - Holtek Semiconductor Inc |
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14 / 32 page  Rev. 1.10 14 November 25, 2015 HT9B95A/B/G I2C Serial Interface I2C Operation ThedevicesupportsI2Cserialinterface.TheI2Cbus isforbidirectional,two-linecommunicationbetween differentICsormodules.Thetwolinesareaserial dataline,SDA,andaserialclockline,SCL.Both linesareconnectedtothepositivesupplyviapull-up resistorswithatypicalvalueof4.7kΩ.Whenthebus isfree,bothlinesarehigh.Devicesconnectedtothe busmusthaveopen-drainoropen-collectoroutputs toimplementawired-orfunction.Datatransferis initiatedonlywhenthebusisnotbusy. Data Validity ThedataontheSDAlinemustbestableduringthe highperiodoftheserialclock.Thehighorlowstate ofthedatalinecanonlychangewhentheclocksignal ontheSCLlineisLowasshowninthediagram. START and STOP Conditions • AhightolowtransitionontheSDAlinewhileSCL ishighdefinesaSTARTcondition. • AlowtohightransitionontheSDAlinewhileSCL ishighdefinesaSTOPcondition. • STARTandSTOPconditionsarealwaysgenerated bythemaster.Thebusisconsideredtobebusyafter theSTARTcondition.Thebusisconsideredtobe freeagainacertaintimeaftertheSTOPcondition. • ThebusstaysbusyifarepeatedSTART(Sr)is generatedinsteadofaSTOPcondition.Insome respects,theSTART(S)andrepeatedSTART(Sr) conditionsarefunctionallyidentical. P S SDA SCL SDA SCL STARTcondition STOPcondition Byte Format EverybyteputontheSDAlinemustbe8-bitlong. Thenumberofbytesthatcanbetransmittedper transferisunrestricted.Eachbytehastobefollowed byanacknowledgebit.Dataistransferredwiththe mostsignificantbit,MSB,first. S or Sr P or Sr SDA SCL 1 2 7 8 9 ACK 1 2 3-8 9 ACK P Sr Acknowledge • Each bytes of eight bits is followed by one acknowledgebit.ThisAcknowledgebitisalow levelplacedonthebusbythereceiver.Themaster generates anextraacknowledge relatedclock pulse. • Aslavereceiverwhichisaddressedmustgenerate anAcknowledge,ACK,afterthereceptionofeach byte. • Thedevicethatacknowledgesmustpulldownthe SDAlineduringtheacknowledgeclockpulseso thatitremainsstablelowduringthehighperiodof thisclockpulse. • Amasterreceivermustsignalanendofdatatothe slavebygeneratinganot-acknowledge,NACK, bitonthelastbytethathasbeenclockedoutof theslave.Inthiscase,themasterreceivermust leavethedatalinehighduringthe9thpulsetonot acknowledge.ThemasterwillgenerateaSTOPor repeatedSTARTcondition. S 1 2 7 8 9 clockpulsefor acknowledgement DataOutput byTransmitter DataOutptu byReceiver SCLFrom Master acknowledge notacknowledge START condition Slave Addressing • Theslaveaddressbyteisthefirstbytereceived followingtheSTARTconditionformthemaster device.Thefirstsevenbitsofthefirstbytemake uptheslaveaddress.Theeighthbitdefinesaread orwriteoperationtobeperformed.WhentheR/W bitis“1”,areadoperationisselected.WhentheR/ Wbitis“0”,awriteoperationisselected. • TheHT9B95deviceaddressbitsare“0111110”. Whenanaddressbyteissent,thedevicecompares thefirstsevenbitsaftertheSTARTcondition.If theymatch,thedeviceoutputsanAcknowledgeon theSDAline. Slave Address 0 1 1 1 1 1 0 MSB LSB R/W |
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