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HT68F003 Datasheet(PDF) 36 Page - Holtek Semiconductor Inc |
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HT68F003 Datasheet(HTML) 36 Page - Holtek Semiconductor Inc |
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36 / 119 page  Rev. 1.41 36 April 11, 2017 Rev. 1.41 37 April 11, 2017 HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM HT68F002/HT68F0025/HT68F003 Cost-Effective Flash MCU with EEPROM Control Register Asingleregister,SMOD,isusedforoverallcontroloftheinternalclockswithinthedevice. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK R/W R/W R/W R/W — R R R/W R/W POR 0 0 0 — 0 0 1 1 Bit7~5 CKS2 ~ CKS0:ThesystemclockselectionwhenHLCLKis"0" 000:fL(fLIRC) 001:fL(fLIRC) 010:fH/64 011:fH/32 100:fH/16 101:fH/8 110:fH/4 111:fH/2 Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.In additiontothesystemclocksource,whichcanbetheLIRC,adividedversionofthe highspeedsystemoscillatorcanalsobechosenasthesystemclocksource. Bit4 Unimplemented,readas"0" Bit3 LTO:Lowspeedsystemoscillatorreadyflag 0:Notready 1:Ready Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeed systemoscillatorisstableafterpoweronresetorawake-uphasoccurred.Theflag willbelowwhenintheSLEEP0mode,butafterawake-uphasoccurredtheflagwill changetoahighlevelafter1~2cyclesiftheLIRCoscillatorisused. Bit2 HTO:Highspeedsystemoscillatorreadyflag 0:Notready 1:Ready Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeed systemoscillatorisstable.Thisflagisclearedto"0"byhardwarewhenthedeviceis poweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatoris stable.Thereforethisflagwillalwaysbereadas"1"bytheapplicationprogramafter devicepower-on. Bit1 IDLEN:IDLEModeControl 0:Disable 1:Enable ThisistheIDLEModeControlbitanddetermineswhathappenswhentheHALT instructionisexecuted.Ifthisbitishigh,whenaHALTinstructionisexecutedthe devicewillentertheIDLEMode.IntheIDLE1ModetheCPUwillstoprunning butthesystemclockwillcontinuetokeeptheperipheralfunctionsoperational,if FSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstop inIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALT instructionisexecuted. Bit0 HLCLK:SystemClockSelection 0:fH/2~fH/64orfL 1:fH ThisbitisusedtoselectifthefHclockorthefH/2~fH/64orfLclockisusedasthe systemclock.WhenthebitishighthefHclockwillbeselectedandiflowthefH/2~ fH/64orfLclockwillbeselected.WhensystemclockswitchesfromthefHclocktothe fLclockandthefHclockwillbeautomaticallyswitchedofftoconservepower. |
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