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UVLO (Buck Controllers)

Current Limit (Buck Controllers)

I

LIMIT

+

V

IS1,2

R

1,2

(1)

I

RMS

V

OUT

V

IN

P

DISS

2

@ R

(2)

Short-Circuit Protection (Buck Controllers)

Soft-Start (Buck Controllers)

TPS75003

SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004

An under-voltage lockout circuit is present to prevent turning on the external PMOS (Q1 or Q2) until a reliable

operating voltage is reached on the appropriate regulator (IN1 or IN2). This prevents the buck controllers from

mis-operation at low input voltages.

An external resistor (R1 or R2) is used to set the current limit for the external PMOS transistor (Q1 or Q2). These

resistors are connected between IN1 and IS1 (or IN2 and IS2) to provide a reference voltage across these pins

that is proportional to the current flowing through the PMOS transistor. This reference voltage is compared to an

internal reference to determine if an over-current condition exists. When current limit is exceeded, the external

PMOS is turned off for the minimum off-time. Current limit detection is disabled for 10ns any time the PMOS is

turned on to avoid triggering on switching noise. In 100% duty cycle mode, current limit is always enabled.

Equation 1:

The current limit resistor must be appropriately rated for the dissipated power determined by its RMS current

calculated by Equation 2:

protect external components such as the inductor, the diode, and the switch itself from damage as a result of

over-current.

In an overload condition, the current rating of the external components (PMOS, diode, and inductor) can be

exceeded. To help guard against this, the TPS75003 increases its minimum off-time when the voltage at the

increased to approximately 4

µs. The increase in off-time is proportional to the difference between the voltage at

the feedback pin and the internal reference.

The buck controllers each have independent soft-start capability to limit inrush during start-up and to meet timing

requirements of the Xilinx Spartan-3 FPGA. Limiting inrush current by using soft-start, or by staggering the

turn-on of power rails, also guards against voltage drops at the input source due to its output impedance. Refer

to the soft-start circuitry shown in Figure 23 and the soft-start timing diagram shown in Figure 24. BUCK 1 will be

discussed in this section; it is identical to BUCK2. Note that pins SS1 and SS2 are very high-impedance and

cannot be probed using a typical oscilloscope setup. When input voltage is applied at IN1 and EN1 is driven low,

any charge on the SS pin is discharged by an on-chip pull-down transistor. When EN1 is driven high, an on-chip

the voltage across the current sense resistor R1 to determine if an over-current condition exists. If the voltage

drop across the sense resistor goes above the reference voltage, then the external PMOS is shut off for the

minimum off-time. This implementation provides a cycle-by-cycle current limit and allows the user to program the

the section, Selecting the Soft-Start Cap.

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