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TPS75003 Datasheet(PDF) 2 Page - Texas Instruments

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Part # TPS75003
Description  Triple-Supply Power Management IC for Powering FPGAs and DSPs
PDF  24 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS75003 Datasheet(HTML) 2 Page - Texas Instruments

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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
TPS75003
SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
SPECIFIED
PACKAGE-LEAD
ORDERING
TRANSPORT
PRODUCT
VOUT
TEMPERATURE
DESIGNATOR
NUMBER
MEDIA, QUANTITY
RANGE, TA
Buck1: Adjustable
TPS75003
Buck2: Adjustable
4.5x3.5 QFN-20 (RHL)
-40
°C to +85°C
TPS75003RHLR
Tape and Reel, 3000
LDO: Adjustable
over operating free-air temperature range (unless otherwise noted)(1)
TPS75003
UNIT
VINX range (IN1, IN2, IN3)
-0.3 to +7.0
V
VENX range (EN1, EN2, EN3)
-0.3 to VINX +0.3
V
VSWX range (SW1, SW2, SW3)
-0.3 to VINX +0.3
V
VISX range (IS1, IS2, IS3)
-0.3 to VINX +0.3
V
VOUT3 range
-0.3 to +7.0
V
VSSX range (SS1, SS2, SS3)
-0.3 to VINX +0.3
V
VFBX range (FB1, FB2, FB3)
-0.3 to +3.3
V
Peak LDO output current (IOUT3)
Internally limited
—
Continuous total power dissipation
See Dissipation Ratings Table
—
Junction temperature range, TJ
-55 to +150
°C
Storage temperature range
-65 to +150
°C
ESD rating, HBM
2
kV
ESD rating, CDM
500
V
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
DERATING FACTOR
TA ≤ 25°C
TA = 70°C
TA = 85°C
BOARD
RΘJC
RΘJA
ABOVE TA = 25°C
POWER RATING
POWER RATING
POWER RATING
Reference
—
—
—
—
—
—
Layout(1)
(1)
Refer to PCB Layout section. Internal power dissipation limits are determined by LDO operation: PDISS = (VIN3– VOUT3) x IOUT3.
2



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