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M058SSAN Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers

Part # M058SSAN
Description  32-bit Microcontroller
PDF  72 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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M058SSAN Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers

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NuMicro M058S Series Datasheet
Nov. 27, 2014
Page 9 of 72
Rev.1.03
Multiple clock sources
Supports wake-up from Power-down or Sleep mode
Interrupt or reset selectable on watchdog time-out
Time-out reset delay period time can be selected
WWDT (Window Watchdog Timer)
6-bit down counter with 11-bit prescale for wide range window selected
PWM
Up to two built-in 16-bit PWM generators, providing four PWM outputs or two
complementary paired PWM outputs
Individual clock source, clock divider, 8-bit pre-scalar and dead-zone generator for
each PWM generator
PWM interrupt synchronized to PWM period
16-bit digital Capture timers (shared with PWM timers) with rising/falling capture inputs
Supports capture interrupt
Additional functions
Internal 10 kHz to PWM clock source
Polar inverse function
Center-aligned type function
Timer duty interrupt enable function
Two kinds of PWM interrupt period/duty type selection
Period/duty trigger ADC function
UART
Programmable baud-rate generator
Buffered receiver and transmitter, each with 16 bytes FIFO
Optional flow control function (CTS and RTS)
Supports IrDA(SIR) function
Supports RS485 function
Supports LIN function
SPI
Supports Master/Slave mode
Full-duplex synchronous serial data transfer
Provides 3 wire function
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Supports Byte Suspend mode in 32-bit transmission
Additional functions
 PLL clock source
 4-level depth FIFO buffer for better performance and flexibility in SPI Burst
Transfer mode
I
2C
Up to two sets of I2C device
Supports master/slave mode
Bidirectional data transfer between master and slave
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via



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