89C52 datasheet(24/50 Pages) ISSI

24 / 50 page

IS89C52

Integrated Silicon Solution, Inc. — 1-800-379-4774

MC013-1C

11/21/98

ISSI®

As data bits come in from the right, 1s shift to the left. When

the start bit arrives at the leftmost position in the shift

Control block to do one last shift, load SBUF and RB8, and

set RI. The signal to load SBUF and RB8 and to set RI is

generated if, and only if, the following conditions are met

at the time the final shift pulse is generated.

1) RI = 0 and

2) Either SM2 = 0, or the received stop bit =1

If either of these two conditions is not met, the received

frame is irretrievably lost. If both conditions are met, the

stop bit goes into RB8, the eight data bits go into SBUF,

and RI is activated. At this time, whether or not the above

conditions are met, the unit continues looking for a 1-to-0

transition in RXD.

More About Modes 2 and 3

Eleven bits are transmitted (through TXD), or received

(through RXD): a start bit (0), eight data bits (LSB first), a

programmable ninth data bit, and a stop bit (1). On

transmit, the ninth data bit (TB8) can be assigned the value

of 0 or 1. On receive, the ninth data bit goes into RB8 in

SCON. The baud rate is programmable to either 1/32 or

1/64 of the oscillator frequency in Mode 2. Mode 3 may

have a variable baud rate generated from Timer 1.

Figures 17 and 18 show a functional diagram of the serial

port in Modes 2 and 3. The receive portion is exactly the

same as in Mode 1. The transmit portion differs from Mode

1 only in the ninth bit of the transmit shift register.

Transmission is initiated by any instruction that uses SBUF

as a destination register. The "write to SBUF" signal also

loads TB8 into the ninth bit position of the transmit shift

is requested. Transmission commences at S1P1 of the

machine cycle following the next rollover in the divide-by-

16 counter. Thus, the bit times are synchronized to the

divide-by-16 counter, not to the "write to SBUF" signal.

The transmission begins when SEND is activated, which

puts the start bit at TXD. One bit timer later, DATA is

activated, which enables the output bit of the transmit shift

after that. The first shift clocks a 1 (the stop bit) into the

ninth bit position of the shift register. Thereafter, only 0s

are clocked in. Thus, as data bits shift out to the right, 0s

are clocked in from the left. When TB8 is at the output

position of the shift register, then the stop bit is just to the

left of TB8, and all positions to the left of that contain 0s.

This condition flags the TX Control unit to do one last shift,

then deactivate SEND and set TI. This occurs at the

eleventh divide-by-16 rollover after "write to SBUF".

Reception is initiated by a 1-to-0 transition detected at

RXD. For this purpose, RXD is sampled at a rate of 16

times the established baud rate. When a transition is

detected, the divide-by-16 counter is immediately reset,

and 1FFH is written to the input shift register.

At the seventh, eighth, and ninth counter states of each bit

time, the bit detector samples the value of RXD. The value

accepted is the value that was seen in at least two of the

three samples. If the value accepted during the first bit time

is not 0, the receive circuits are reset and the unit continues

looking for another 1-to-0 transition. If the start bit proves

valid, it is shifted into the input shift register, and reception

of the rest of the frame proceeds.

As data bits come in from the right, 1s shift out to the left.

When the start bit arrives at the leftmost position in the shift

the RX Control block to do one last shift, load SBUF and

RB8, and set RI. The signal to load SBUF and RB8 and to

set RI is generated if, and only if, the following conditions

are met at the time the final shift pulse is generated:

1) RI = 0, and

2) Either SM2 = 0 or the received ninth data bit = 1

If either of these conditions is not met, the received frame

is irretrievably lost, and RI is not set. If both conditions are

met, the received ninth data bit goes into RB8, and the first

eight data bits go into SBUF. One bit time later, whether the

above conditions were met or not, the unit continues

looking for a 1-to-0 transition at the RXD input.

Note that the value of the received stop bit is irrelevant to

SBUF, RB8, or RI.

Table 10. Serial Port Setup

Mode

SCON

SM2Variation

10H

50H

90H

D0H

0NA

70H

B0H

F0H

Single Processor

Environment

(SM2 = 0)

Multiprocessor

Environment

(SM2 = 1)

89C52 Datasheet(PDF) 24 Page - Integrated Silicon Solution, Inc

89C52 Datasheet(HTML) 24 Page - Integrated Silicon Solution, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL