WM8501

Production Data

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PD, Rev 4.3, February 2013

18

PCB LAYOUT RECOMMENDATIONS

Care should be taken in the layout of the PCB that the WM8501 is to be mounted to. The

following notes will help in this respect:

1.

The VDD supply to the device should be as noise free as possible. This can be

accomplished to a large degree with a 10uF bulk capacitor placed locally to the device and a

0.1uF high frequency decoupling capacitor placed as close to the VDD pin as possible. It is

best to place the 0.1uF capacitor directly between the VDD and GND pins of the device on

the same layer to minimize track inductance and thus improve device decoupling

effectiveness.

2.

The VMID pin should be as noise free as possible. This pin provides the decoupling for

the on chip reference circuits and thus any noise present on this pin will be directly coupled

to the device outputs. In a similar manner to the VDD decoupling described above, this pin

should be decoupled with a 10uF bulk capacitor local to the device and a 0.1uF capacitor as

close to the VMID pin as possible.

3.

Separate analogue and digital track routing from each other. The device is split into

analogue (pins 5 – 9) and digital (pins 1 – 4 and pins 10 – 14) sections that allow the routing

of these signals to be easily separated. By physically separating analogue and digital

signals, crosstalk from the PCB can be minimized.

4.

Use an unbroken solid GND plane.

To achieve best performance from the device, it is

advisable to have either a GND plane layer on a multilayer PCB or to dedicate one side of a

2 layer PCB to be a GND plane. For double sided implementations it is best to route as

many signals as possible on the device mounted side of the board, with the opposite side

acting as a GND plane. The use of a GND plane greatly reduces any electrical emissions

from the PCB and minimizes crosstalk between signals.